Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20623 Discussions

PCIE link training fails. host doesn't send TS1/TS2 order set after reset.

Altera_Forum
Honored Contributor II
1,613 Views

device Arria 10 660  

The PCIE core and PHY are generated together using Quarters. 

 

We use PCIE analyzer adapter card to capture the training sequence. The host has never sent out TS1/TS2. The LTSSM state jumps between 0,1,2.  

It seems that the host has never detected our device so it keeps silence. But we checks the board connection and IO assignment. We can't find anything wrong so far.  

Could someone give me some hint? thanks
0 Kudos
0 Replies
Reply