Remote hardware debugging through SLD Hub Controller IP

[Altera_Forum]

Hello, 

 existing hardware debug examples are using "SLD Hub Controller System" IP to expose a MM interface to JTAG debug functions. It's internally translated to ST interface. Alternatively "SLD Hub Controller" IP allows to directly access SLD hub with a byte-wide ST interface.   Unfortunately there's no further documentation or an application example showing the intended usage of the SLD Hub Controller streaming interface. Does anybody know why SLD Hub Controller with ST interface is provided as a separate component?  The streaming interface seems suitable in a distributed system where the JTAG debug functions of a slave FPGA shall be accessed through a serial link and a master FPGA. Question is if we can link it directly to the remote debug TCP interface if the necessary sop/eop escape translation is applied? Or are additional translations required?  Best regards, Frank

[Altera_Forum]

Hi Frank, 

 Does AN-693 have the details you need:  https://www.altera.com/support/literature/lit-an.html  The apps note page has a link to the PDF and Linux drivers ... but the drivers are a kernel module .ko module only. The PDF provides details on the driver source location (on rocketboards.org).  Perhaps this is sufficient for what you were interested in doing ... personally I'd prefer to see a document with the protocol published.  Perhap the driver source code is sufficient for what you want. It is possible that the driver just forwards the content of Ethernet packets down to the JTAG chain. Wireshark would allow you to see the Ethernet packet format.  Chances are the SLD HUB protocol has not changed much from the JTAG-only version ... scroll down to the JTAG-to-Avalon-MM/ST and Virtual JTAG analysis docs: https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 thanks for your substantial responce.   To clarify my point, I have no problems to understand the implementation using the Linux driver and interfacing "SLD Hub Controller System" through Avalon MM. I was basically asking if there are any examples for using the "SLD Hub Controller" Avalon ST interface. Or in other words wondering why Altera exposed a third interface besides bit level "Soft core JTAG IO" and Avalon MM.  Background is that I'm adding remote hardware debugging to processor-less FPGA slave systems and want to embed the debug link in an existing serial high speed connection. After a brief analysis of the "SLD Hub Controller System" IP, it looks like we can cut it in the middle and connect through serial link. Or use the Avalon ST interface as is and add the necessary sop/eop translation and a FIFO.    --- Quote Start ---  personally I'd prefer to see a document with the protocol published  --- Quote End ---   Same old story with missing Altera documentation.    --- Quote Start ---  Perhaps the driver source code is sufficient for what you want. It is possible that the driver just forwards the content of Ethernet packets down to the JTAG chain. Wireshark would allow you to see the Ethernet packet format.  --- Quote End ---   It obviously does. A colleague who's working on the microprocessor project part already confirmed this. Just shuffling the TCP stream bytes to and from the (byte-wide utilized) MM data register, controlled by FIFO level. And processing a few out-of-band requests like reset that aren't related to SLD Hub communication.   I see that you have done a great job in documenting the virtual JTAG protocol. Parts of the protocol like the bytes-to-packet command codes used in JTAG-to-Avalon-MM protocol are reused in the Avalon MM to SLD Hub communication. So your analysis can surely help me.  Best regards, Frank

[Peter01]

Hi Frank,

" I'm adding remote hardware debugging to processor-less FPGA slave systems"

Had you able to achieve your above requirement ?

I also want to establish a remote debugging to  processor-less FPGA using signal tap.

Your suggestion would be highly appreciated.

Thank you

[Altera_Forum]

Hi Frank, 

   --- Quote Start ---   So your analysis can surely help me   --- Quote End ---   Great! The JTAG-to-Avalon-MM tutorial has a Tcl script that implements the protocol under quartus_stp. That Tcl should have pretty much all you need to implement the protocol.  I used Kawk's reverse-engineering of the USB-Blaster to duplicate that logic and wrote some C-code to access the device via the FTDI driver ... It works, but unfortunately does not play nicely with the Altera tools, since each JTAG access needs to manipulate the TAP state. Eventually I decided there were more useful things to be doing with my time :)  Cheers, Dave

[FvM]

Hi Peter,
can tell that I was finally able to implement FPGA based remote debug connection. The solution depends of course on the communication infrastructure available in your distributed system. And there must be an endpoint that can be connected to PC host. 

For JTAG server interface, I took advantage from this project https://github.com/j-marjanovic/jtag-quartus-ft232h

I also commented your questions about SLD Hub Controller in your recent thread https://community.intel.com/t5/FPGA-Intellectual-Property/Use-case-of-SLD-hub-controller/td-p/1576202

Regards
Frank

[Peter01]

Hi Frank,

Thank you for suggestions.

I have looked out  this solution : "For JTAG server interface, I took advantage from this project https://github.com/j-marjanovic/jtag-quartus-ft232h"

 so are you using  a FT232H at the FPGA end ?

[FvM]

Hi Peter,
I'm not using FT2232H in my remote debug solution.
I used the mentioned project as a template to design my own JTAG_HW_xxx.dll

Regards

Frank  

[Peter01]

Hi Frank,

Wow, replacing FT2232H is a  marvelous job.

Could you please help to implement FPGA based remote debug connection.

Thank you