I have a custom board which is based on the FSM shared bus design. where a Cyclone 5 and Max 5 share a 16 bit data and 26 bit address bus and control signals. connected to this bus is a Numonyx PC28F00AP30BFA 1G-bit CFI flash.
In QSYS I have a jtag to Avalon master bridge connected to a generic tri-state controller which in turn is connected to a tri-state conduit bridge. The timings with the CFI Pre select are all set to 0so I have set the timings to the ones I found on a reference design( uses the same flash family but is a 512Mb). with these settings I can read from flash using system console however when I do a write and read back nothing is written. I have connected signal tap to the Wen Oen, Cen, data and address busses aswell as physically looking at these pins with a scope. they match, so I'm confident that the signals are leaving the board.
I have looked at the Generic tri-state controller data sheet from altera and on page 2-4 it describes what each signal means. however the description is different to what the datasheet for the flash says. so i am confused to know what values I need. would some one be able to tell me the follow timings.
Read wait time
write wait time
setup wait time
data holdtime
maximum pending read transactions
turn around time
read latency,
could there be any other reasons why the flash is not being written to ?
