Some basic questions about DDR

[Altera_Forum]

Hi all, 

  I am studying the RTL based example code of LPDDR2 demonstration of Cyclone V 5CGXFC5C6 development kit from Terasic.   Basically, this demo code utilizes a LPDDR2 IP, and then write in-->read back all address to verify the whole memory, according to the statement of the user manual.    The LPDDR2 is a 16M x 32 x 8banks chip, with 32 DQ signals all connected to FPGA, as listed in the figure "lpddr2 circuit" in attachment;    The code has also been attached in case you are interested, with "(top level)c5g_lpddr2_rtl_test.v", and "(test part)avalon_bus_rw_test.v";  the diagram of the whole project is illustrated using the figure "project structure",    I also made a figure "signal connection" to illustarte the signal connections internal and external for the ease to understand, and save your time;   The settings of the LPDDR2 IP is listed in figure "ip setting_1","ip setting_2" and "ip setting_3";     I have spent several weeks on the code and reading a lot of datasheets, still with some confusions.   (1) The UNIPHY-Mem interface, DQ, is 32-bit, and in 'IP Setting_1', the Avalon-MM interface is set as "Full Rate", why generated IP data width of Avalon is still 32-bit?    output wire [31:0] avl_rdata_0, // .readdata  input wire [31:0] avl_wdata_0, // .writedata   They should be 64-bit, right? Since UNIPHY-Mem is 32 bit with DDR, AFI (only can be single data rate) with Full rate should be 64-bit. Right? What am I missing?   (2) In 'IP Setting_2', it sets the 'Mode Register 1--Burst length' to 8; here should be UNIPHY-Mem interface;   In 'IP Setting_3', it sets 'Maxium Avalon-MM Burst length' to 4; here should be external-controller interface;  In the code, it sets Avl_size to 1;   Literally, I understand what does 'Burst' mean; but here, does 'Mode Register 1--Burst length = 8' mean, any read/write between UNIPHY and memory, must be in 8-word(32bit/word) unit? And although Avalon burst is set to 4, but actually Avl_size has limited this Avalon burst length to only 1, right?   (3) Why the code uses afi_half_clk, not afi_clk, to read/write to/from the controller? This really confuses me. The Avalon interface is set as full-rate SDR with 32bit, but the code uses half rate clock still with 32bit to read/write, why? Why it doesn't use afi_clk?   My questions are pretty long, thanks so much for your time and patience, and really appreciate if you can give me any hint~~   Regards,

[Altera_Forum]

IP Settings here

[Altera_Forum]

I just found that if I de-select the "Enable Hard External Memory Interface" in figure "IP Setting_1", then the data width of avl_rdata and avl_wdata will comply with the rule: Full rate -- x2; Half rate -- x4. 

 If I select this feature, then I can only select "Full rate", and data bus would be 32, the same with DQ width of memory chip.  So, what is going on here?

[Altera_Forum]

first... is this hdl compilation success?