QII configures D3 & D1 delay chains incorrectly for ALTDDIO in IOE - Tsu/Th err

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

QII configures D3 & D1 delay chains incorrectly for ALTDDIO in IOE - Tsu/Th err

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I posted this for better description of the problem. Please see below post for detailed technical description.

http://www.alteraforum.com/forum/showthread.php?t=48866 (http://www.alteraforum.com/forum/showthread.php?t=48866)

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