Cyclone V GX Transceiver CDR clock acquisition time

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cyclone V GX Transceiver CDR clock acquisition time

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I'm working on a TDD burst application. I plan on using the GX Transceivers at a 1.25Gbps rate. When a serial stream is applied, what is the clock acquisition time?

I plan on bypassing the PCS section. I just want to recover the clock from the data.

Thanks,

-j

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