Incremental Compilation and SignalTap

[Altera_Forum]

Hi all, 

 My understanding is that we cannot preserve the placement & routing if we create a new partition under the top-level design (which is a partition by default). In this case, how does the PostFit signaltap work since we are essentially adding 2 new partitions (sld_hub & sld_signaltap) under the top-level design. Is PostFit signaltap an exception in this case?   In order to really preserve the P&R of the design, do I need to set to Top partition to post-fit IN ADDITION to adding PostFit signaltap?  How do I confirm that the P&R of the design is not changed besides looking at the 'Incremental Compilation Section' in the Fitter report?

[Altera_Forum]

Arria 10 or another family? For Arria 10 Standard edition, I do not believe routing is preserved. For all other families you should be able to preserve both placement and routing. Assuming Top is your only partition, set it to post-fit placement and routing. SignalTap is automatically another partition/s, you don't have to do anything special, and it will be fit around the existing design. (You should also try Processing -> Start -> Rapid Recompile if it's supported for your device, as this is meant to do a very similar thing of keeping your design locked down and fitting signaltap, but it has some extra capabilities such as handling design changes, and I believe is the "future flow" for quick SignalTap compiles.) For Arria 10, it all holds true except the design must re-route, which hopefully doesn't cause the problem to go away.

[Altera_Forum]

I was referring to normal devices ( I wasnt aware Arria10 is not able to preserve its routing). That leads me to another question, in order to preserve the P&R of entire design, do I need to also set the other sub-partitions to PostFit or only the Top to Postfit + other partitions under it to SourceFile will just work fine? 

 Besides source files, what other changes will break the post-fit preservation? I believe SDC file changes will. How about fitter settings (i.e seed sweep, routing/placement effort, physical synthesis). Which will take precedence?

[Altera_Forum]

The two reasons to do post-fit on your logic with SignalTap are: 

a) Faster compile times b) Preserving the placement and routing when there is a bug that comes and goes depending on the place and route. When you set a partition to post-fit, there is an option to Ignore Changes in Source File. If you do that, then changing the seed/.sdc/etc. will not get a new place-and-route. If you don't have this set, then Quartus will try to be smart and will start from source if it thinks it needs to, specifically if there is a change in the source code. I'm not sure about the other things.  Generally for a SignalTap flow where you want a) and/or b), you would set all of your partitions to post-fit and would not change anything else in the design(your debugging the existing fit, not adding changes), and therefore there are no changes for it to figure out. If you are making changes to the design, then I generally don't set it to post-fit. Basically I don't ever rely on it knowing what to do, not that it doesn't work, but I know enough of whether I want everything locked down or not that I don't need it to be smart. That's the flow I've seen most used.

[Altera_Forum]

I am usually most interested in part b), where I would need to preserve the P&R of the entire design. In many cases particularly in huge design, when I set the top partition to post-fit and recompile, I would face fitter error, usually indicating resource conflict or not being able to satisfy hard routing constraints. This prevents me from preserving the netlist of the design.  

 I presume if I do not set the top-partition to PostFit but add Postfit STP, only the tapped signals will be preserved, but the rest of the design is still free to move?

[Altera_Forum]

I experimented with incremental compilation on my designs in order to save build time. Found that full build actually took few minutes longer, because the process of merging partitions was quite slow. 

Those were Arria10 designs with post-fit partitions; original build took between 40min to 1.5hours.

[Altera_Forum]

That's not good. For skyjuice, the PostFit filter in SignalTap is only a filter for finding node names and has no affect on what's done in the next compile. Quite often the same node name(such as a register) can be found in pre-synthesis, post-syntesis, post-fit SignalTap, etc. filters in SignalTap and they all act the same. If you want to preserve it's location then you need to use partitions. (Also, don't forget about trying Rapid Recompile) 

Note that most of the time you don't need b), as most issues are functional issues that should occur even if everything is placed-and-routed again. The main time b) comes up is with incorrect design/timing constraints, such as something that is incorrectly false path'd, and on one fit it happens to meet timing and work while on another fit it doesn't, but you never know because you false path'd it. SignalTap is invaluable for tracking these things down, but most problems don't fall into this category. (Or at least hopefully they don't and I would revisit your timing constraint methodology...)

[Altera_Forum]

Thanks for the input, Rysc. Too bad most of the time I need to preserve then entire P&R of the design while adding STP as I am dealing with some users' timing constraints. Just trying my luck to see if there is any other solution for this besides setting the top partition to post-fit which usually results in fitting error, and it seems the answer is no.

[Altera_Forum]

Did you try Post Fit Placement only to see if that fits? There will be some variability due to re-routing the design, but it's much smaller than doing a full place-and-route from scratch. Or run a few seeds from scratch with SignalTap in there. Hopefully one of them exhibits the problem. Now that STP is in there, it also might be easier to change your tap points and do Post-Fit on the rest(although I don't know why it's not fitting, so can't say for sure one way or the other).

[Altera_Forum]

Along the lines of Rapid Recompile, I obtained the networked license file from my university. It seems to contain licenses for different IP, but I don't specifically see "Rapid Recompile." 

 Is "Rapid Recompile? a specific product?  The option (Processing -> Start -> Rapid Recompile) is grayed out for me. I had assumed before obtaining our university license that any paid license would come with it. Am I wrong?