VHDL2008 matching equality operator

[Altera_Forum]

i can't get VHDL-2008 matching equality operator compiled on quartus2.  

when i compile the code below it says: Error (10327): VHDL error at test.vhd(13): can't determine definition of operator ""?="" -- found 0 possible definitions  'VHDL 2008' option is being chosen on Assignments > Settings > Complier Settings > VHDL input setting . wondering what i have done wrong. any suggestions? thanks.  code:library ieee; use ieee.std_logic_1164.all;  entity test is  port(  a,b: in std_logic_vector(3 downto 0);  y: out std_logic_vector  &nbsp;); end test;  architecture rtl of test is  begin  y <= a ?= b;  end rtl;     quartus2 version : Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition

[Altera_Forum]

My understanding is that the type ?= returns is the smallest element from the comparation. so in this case std_logic. You try to assign this to a vector. I could be wrong, but does changing the type of y work? 

 [edit]Reread the specs, it returns ulogic[/edit]

[Altera_Forum]

y need to be a std_logic, not a std_logic_vector. 

?= returns a single bit.  If it has to be a vector, maybe try:  y(0) <= a ?= b;

[Altera_Forum]

Thanks for the replies! 

 Actually what I did at the first place was declaring y as std_logic, but seems it somehow got messed up when I copied the code to the thread. ('&nbsp' appeared as burried backspaces in the source file? I don't know).   I also had tried std_ulogic(_vector) but no difference.  I tried the following code just in case but again got the same error message for both y and z(0).    library ieee; use ieee.std_logic_1164.all;  entity meqtest is  port(  a,b: in std_logic_vector(2 downto 0);  y: out std_logic;  z: out std_logic_vector(1 downto 0)  ); end meqtest;  architecture rtl of meqtest is  begin  y <= a ?= b;  z(0) <= a ?= b;  end rtl;   Thanks again,

[Altera_Forum]

It could be the fact that Quartus VHDL 2008 support is far from complete. The matching equality operator is also implicitly used when you use the following code: 

  a : std_logic; .... if a then   They may mean they only support this form. Otherwise, raise a support ticket for better 2008 support? Does the code compile fine in Modelsim?

[Altera_Forum]

Hi Tricky, 

 Tried Modelsim (starter 10.3d) and it turned out it's not happy with the code as well, saying :  Signal "a" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC.  I double checked the the env variable VHDL93 has been chanted to 2008 in modelsim.ini file.   It looks pretty much like what you've said. I'll raise a flag to Altera.  Thanks for your help.

[Altera_Forum]

I just compiled your code in Modelsim, and it works just fine. The errors you get pop out if you are compiling in 93 mode. 

You can compile each file with a specified VHDL version:  vcom meqtest.vhd -2008  And it compiles just fine.

[Altera_Forum]

Just tried as you indicated in Modelsim and got it working. Thanks a lot!  

also sent a feedback to altera. hope it's supported in Q2.