Impossible to do ECO on DE1-SoC (Cyclone V)

[Altera_Forum]

Hi, 

 I have a very simple design for a Cyclone V SoC on a DE1-SoC board - a minimal Qsys system based on the Computer System provided within the Altera University Program but with just the interface to the HPS, the GPIOs to the board LEDs and 7 segments displays and an extremely simple custom accelerator. The system compiles and works; however, any time I try to do even the simplest ECO change, like changing one bit in an LUT mask or moving a flip flop within the same logic element, I get 100+ errors such as:  Error (129001): Input port ENA on atom "Computer_System:The_System|Computer_System_ARM_A9 _HPS:arm_a9_hps|Computer_System_ARM_A9_HPS_hps_io: hps_io|Computer_System_ARM_A9_HPS_hps_io_border:bo rder|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p 0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs: dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev:altdq_dqs2_inst|dqs_config_gen[0].dqs_config_inst", which is a cyclonev_dqs_config primitive, is not legally connected and/or configured Info (129003): Input port ENA is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Error (129001): Input port UPDATE on atom "Computer_System:The_System|Computer_System_ARM_A9 _HPS:arm_a9_hps|Computer_System_ARM_A9_HPS_hps_io: hps_io|Computer_System_ARM_A9_HPS_hps_io_border:bo rder|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p 0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs: dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev:altdq_dqs2_inst|dqs_config_gen[0].dqs_config_inst", which is a cyclonev_dqs_config primitive, is not legally connected and/or configured Info (129003): Input port UPDATE is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Error (129001): Input port DATAIN on atom "Computer_System:The_System|Computer_System_ARM_A9 _HPS:arm_a9_hps|Computer_System_ARM_A9_HPS_hps_io: hps_io|Computer_System_ARM_A9_HPS_hps_io_border:bo rder|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p 0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs: dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev:altdq_dqs2_inst|pad_gen[1].config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured Info (129003): Input port DATAIN is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal  where Computer_System:The_System is my Qsys top level module. All the errors are related to pins in Computer_System:The_System|Computer_System_ARM_A9_ HPS:arm_a9_hps|Computer_System_ARM_A9_HPS_hps_io:h ps_io|Computer_System_ARM_A9_HPS_hps_io_border:bor der|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p 0_acv_hard_io_pads:uio_pads, even though my ECO changes are always applied to logic belonging to other modules (my accelerator). I'm doing the ECO changes by editing the design from the Chip Planner and clicking on "Check and save all netlist changes". Is there something I'm missing?  Thanks.  Best,  Mikhail