Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Startup Delay

Altera_Forum
Honored Contributor II
‎11-15-2016 11:22 AM
1,267 Views

Hi everyone, 

 

I am using Altera MAX 10 CPLD in my design. I would like to know what is the startup delay associated with the device (the time elapsed between power on and the device starts working). 

 

Thanks in advance :)
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Altera_Forum
Honored Contributor II
‎11-15-2016 12:56 PM
253 Views

Hi, 

 

the start-up time depends on the following factors: 

  • how fast your power supply ramps up 

  • the POR scheme (instant, fast, slow) 

  • the device size 

 

The power supply ramp-up time must be within certain limits (see section "Configuration Details" of the device handbook). The POR scheme can be selected (see section "Initialization Configuration Bits"). Finally, the configuration time depends on the device size (see section "Umcompressed Raw Binary File" of the datasheet). 

 

So in a nutshell, the time between your DC rail reaches its full level and the MAX 10 FPGA enters user mode can be in the range 3..209 ms. 

 

 

Best regards, 

GooGooCluster
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