still problems with timequest

[Altera_Forum]

Studying the AN 477 to page 15 I read: 

At the FPGA (Receive) Side  example 4.# create a 125mhz clock# virtual_source: an ideal clock in the sourcing device# rx_clk: input clock port of the interface; 90 deg phase shifted create_clock -name virtual_source -period 8 create_clock -name rx_clk -period 8 -waveform { 2 6 } [get_ports {rx_clk}]# set input delay based on the requirements mentioned previously# rx_clk is 90 deg phase shifted# input delay is relative to the rising and falling edges of the clock set_input_delay -max 0.8 -clock [get_clocks virtual_source] -add_delay [get_ports rxd*] set_input_delay -min -0.8 -clock [get_clocks virtual_source] -add_delay [get_ports rxd*] set_input_delay -max 0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay  [get_ports rxd*] set_input_delay -min -0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay  [get_ports rxd*] set_input_delay -max 0.8 -clock [get_clocks virtual_source] -add_delay [get_ports  {rx_ctl}] set_input_delay -min -0.8 -clock [get_clocks virtual_source] -add_delay [get_ports  {rx_ctl}] set_input_delay -max 0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay  [get_ports {rx_ctl}] set_input_delay -min -0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay  [get_ports {rx_ctl}]# set false paths to remove irrelevant setup and hold analysis set_false_path -fall_from [get_clocks virtual_source] -rise_to [get_clocks {rx_clk}]  -setup set_false_path -rise_from [get_clocks virtual_source] -fall_to [get_clocks {rx_clk}]  -setup set_false_path -fall_from [get_clocks virtual_source] -fall_to [get_clocks {rx_clk}]  -hold set_false_path -rise_from [get_clocks virtual_source] -rise_to [get_clocks {rx_clk}]  -hold   I use cyclonev dev board with marvell ethernet PHY. I use the phy delay option for center align the rx data to rx clock (from phy to fpga). I replaced the value 0.8 with the value 1.2 (see image).  But timequest analis fails hold slack. where am I wrong?