Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

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Altera_Forum
Honored Contributor II
1,353 Views

Hey! 

 

I'm doing a school project and I got problem which I have hard to solve so I hope for your help. 

Basicly when I try to test my block diagram on my SW[2] output I get undefined value X.  

I really don't know what is wrong in it. But I will add picture of how is diagram looking and what result do I get. 

 

I also will add a ling to my diagram I wanted to look http://tinyurl.com/yaejw9a9 

 

Thanks for all help and I also hope I used right subforum. 

https://alteraforum.com/forum/attachment.php?attachmentid=14401&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14402&stc=1
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Altera_Forum
Honored Contributor II
488 Views

The simulator doesn't know what value, '0' or '1', to give each of your flip flops at the start of simulation. So, it will give each the value of 'Z'. The result of any combinational logic when any of the input values is 'Z' will be 'X'. 

 

In practice (on real hardware) this won't be an issue since all your flip flops will power up as either a '0' or '1' and everything will work. 

 

So, I suggest you modify your code/schematic and introduce a 'reset' signal. When you assert this reset all the flip flops will take a known value ('0' or '1'). You may need to use a slightly different flip flop primitive. The one you've chosen doesn't appear to have a reset. However, there should be one that does. 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
488 Views

All of them have Clrn ports unconnected.

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Altera_Forum
Honored Contributor II
488 Views

Hey 

 

Thanks for your help. First I tried with reset but I actually got same results as before. But I kept in my mind that simulator doesn't know what value it should give at the start of simulation. 

So I added extra PIN in the beginning with '1' value and that solved my problem. I guess it is hard way of doing it but at least it works well now ;) 

 

Just adding the picture of diagram and results I wanted to get (modulo 10). 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14415 https://www.alteraforum.com/forum/attachment.php?attachmentid=14416
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