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I'm new here. Looking to migrate from Obsolete EPCS4SI8N to EPCQ4ASI8N and noticed The Fast Read Dummy Cycles is 8 on the new part while it is only 1 on the obsolete part. If I'm running the New Part at slow speeds, do I still need 8 Dummy Cycles or could I get away with 1 Dummy cycle, (due to the much slower clock speed)? Is it really time I'm waiting fore or is they an internal counter that must step thru 8 dummy cycles? All help greatly appreciated.
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Hi,
You can configure the number of dummy cycles. Check the link for compatibility and timing information. https://www.altera.com/en_us/pdfs/literature/an/an727.pdf http://www.mouser.com/ds/2/612/cfg_cf52012-1098931.pdf Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Thank you. The link to the Altera AN727 does not work, (page not found).
Also, Please keep in mind that I and switching to the EPCQ4ASI8N device, (4AS device). When you say I can configure the number of dummy cycles, how and where do I configure the number of dummy cycles? Thanks in Advance. Mark- Mark as New
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Hi Mark,
Please check the table:29 in below link. http://www.mouser.com/ds/2/612/cfg_cf52012-1098931.pdf. Note:Number of dummy cycles. When this number is from 0001 to 1110, the dummy cycles is from 1 to 14. Check the manual for more information Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Hi Mark,
Check the Link for more information on EPCQ4ASI8N migration. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an822.pdf Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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Hi Mark and Anand,
I have just found out the following part associated with the actual problem in the mentioned AN822 spec: The dummy clock requirement of the fast read (0Bh) and extended quad input fast read (EBh) commands: EPCQ—the dummy clock is configurable with the non-volatile configuration register (NVCR). When the EPCQ is used with a Cyclone® V, Arria® V or Stratix® V device, the dummy clock is configured to be 4, 10 or 12, depending on the byte-addressing mode and ASx1 or ASx4 configuration. However, in EPCQA devices, the dummy clock is fixed at 8 and 6 for fast read and extended quad input fast read respectively. Therefore you must regenerate the programming files, such as .pof, .jic, and .rpd. For further information: AN822 spec, 1.1 Migration Considerations, Operation Commands. Regards, Martin
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