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How to improve the frequency of the running clock of FPGA?

Altera_Forum
Honored Contributor II
‎01-30-2018 07:12 AM
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Hi, 

 

After I compile my OpenCL FPGA code, I find the frequency of the running clock of the kernel is about 130MHz, how to improve it? 

 

Thanks!
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Altera_Forum
Honored Contributor II
‎01-30-2018 02:01 PM
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There is no direct control over operating frequency in OpenCL. Loop-carried dependencies and complex loop exit conditions reduce operating frequency. Also if your design is large with a high logic utilization count, that will complicate routing and reduce operating frequency.

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