Niosll vga output

Altera_Forum · ‎02-19-2018

Hi all,

I am designing a Nios ll classic processor based SOC for DE2-115 , when i studied its .v (soc instantiation) file i noticed that vga controller out ports i.e

output wire [7:0] vga_controller_ext_R, // .R

output wire [7:0] vga_controller_ext_G, // .G

output wire [7:0] vga_controller_ext_B // .B

);

are all 8-bit ???? this is wrong it should be 10-bit as per DE2-115 vga DACs .

i used the Altera UP IPs for creating all components in Quartus prime ver 16.0 .

And i dont see any option to change the width of RGB output on vga controller ???

Any one any idea whats wrong here ???

Regards

Altera_Forum · ‎02-20-2018

Hi,

Yes,ADV7123 is 10 Bits.And it can't be configured has 10 bit in present hardware.

It is used as 8-bit,That is DAC two LSB pins of R,G & B are grounded which shifts DAC offset.

Refer the schematic.

If you want to have R,G & B lower width than 8-bit you can achieve it by making lower LSB to logic 0 in your logic.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)