Dear all,
I would like some clarifications about Interlaken implementation on Altera/Intel FPGA.
I need to implement a single lane communication between two FPGAs on StratixV/ArriaV-GZ at 10-12.5 Gbps and I need a backpressure/flow control system.
Is there any better choice than Interlaken? in my case I am force to use v1, because v2 has min 4 lanes.
Reading the documentation I understand that the PHY is controlled and monitor through Avalon-MM, but Interlaken IP v1 is not available anymore on Platform Designer/Qsys.
Is there any way to use the old Interlaken IP created by Quartus inside a qsys project?
I have already tried the basic examples, but without luck. Some are without an Avalon interface, so they cannot be monitored easily by the Transceiveir toolkit. I believed that an avalon interface was mandatory. Instead I found one example w/o that .
Do you have any additional example that I can try to resue/adapt?
Many thanks for your time,
Riccardo
