Fitter not using right pin assignments

Altera_Forum · ‎03-25-2018

Dear all,

I'm trying to get an lpddr2 memory controller working using the altera ip core megafunction for. I created the IP core, run analysis and elaboration and then the tcl script for the pin assignments. However, I always run into problems when I want to finally synthezise the fpga configuration:

Fitter is making problems:


Critical Warning (169085): No exact pin location assignment(s) for 46 pins of 158 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 DQS Group(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
    Error (175020): The Fitter cannot place logic DQS Group in region (32, 0) to (66, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
        Info (14596): Information about the failing component(s):
            Info (175028): The DQS Group name(s): I/O pad DDR2LP_DQS_p
        Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
            Info (175015): The I/O pad DDR2LP_DM is constrained to the location PIN_AF11 due to: User Location Constraints (PIN_AF11)
                Info (14709): The constrained I/O pad is contained within a pin, which is contained within this DQS Group
            Error (175006): Could not find path between source DLL and the DQS Group
                Info (175026): Source: DLL ram_ip_core:ram_inst1|ram_ip_core_0002:ram_ip_core_inst|altera_mem_if_dll_cyclonev:dll0|dll_wys_m
                Info (175021): The DLL was placed in location DLL_X68_Y58_N3
                Error (175022): The DQS Group could not be placed in any location to satisfy its connectivity requirements
                Info (175029): 1 location affected
                    Info (175029): DQS Group containing Y14
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

Seems to me that fitter has problems connecting the specific elements to output pins for no obvious reasons. I'm using the Terasic Altera Cyclone V GX Starter Board using Cyclone V 5CGXFC5C6F27C7 . . I even have a working lpddr2 example project (C5G_LPDDR2_RTL_Test from Terasic) for the gx board, and only to check for errors I compared the assignment table between the example project and my project, everything is correct.

Do you have any suggestions what could be the reason for these errors?

I attached the project qar file.

Altera_Forum · ‎03-26-2018

The script does not make the pin location assignments for you. All it does is specify the I/O settings (I/O standards, termination, etc.). You still have to assign to specific locations using the Pin Planner.

Altera_Forum · ‎03-28-2018

--- Quote Start ---

The script does not make the pin location assignments for you. All it does is specify the I/O settings (I/O standards, termination, etc.). You still have to assign to specific locations using the Pin Planner.

--- Quote End ---

Ok, I assigned the specific locations using the Pin Planner.

It sill didn't worked.

Then I changed the clock input for the DLL PLL from CLOCK_50_B6A (PIN N_20) to CLOCK_50_B5B (PIN_R20) and now fitter completeted successfully. What is the reason for this? Is the PLL DLL too far away from CLOCK input pin?

What do I need to do to get the design working with CLOCK_50_B6A?

In the working example I can use both clock inputs without problem. Seems to me that fitter fits the design in my project in another way...?