Problem of using Altera Avalon-MM Master Template

[Altera_Forum]

Hi All, 

   Currently I'm trying to make a custom Avalon-MM master to control the slave IP(UART, SPI, DDR controller...etc) on Avalon Bus. After survey the threads in forum and application notes from Altera, I choose the "avalon-mm master template (https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html)" as middle layer for me to access Avalon Bus.  Before doing the fully compilation and program, the first thing I want to make sure is the timing sequence and reaction of Avalon-MM Master Template. According to user manual, my  understanding control sequence for write and read is:   write: 1) reset all control/user signals 2) check if control_done is asserted 3) check if user_buffer_full is de-asserted 4) register the following signals:  -> control_write_base  -> control_write_length  -> control_fixed_location  -> user_buffer_data  assert following signals:  -> control_go  -> user_write_buffer 5) after one clock cycle, de-assert following signals  -> control_go  -> user_write_buffer 6) if user want to keep writing, go back to step 2 7) wrute sequence is completed   read: 1) reset all control/user signals 2) check if control_done is asserted 3) register the following signals:  -> control_read_base  -> control_read_length  -> control_fixed_location  assert following signals::  -> control_go 5) after one clock cycle:  -> de-assert control_go 6) wait until user_data_available is asserted 7) read out data from FIFO  -> Get data from user_buffer_data  -> assert user_read_buffer 8) de-assert user_read_buffer 9) read sequence is completed    I use the "custom_masters_hw.tcl" to generate my own Avalon-MM Master component in Qsys, and using it to connect with other Altera slave IP.  In the practice project, I added an Altera RS232 IP into Qsys and trying to use modeslim to verify the master template's functionality.  The testbench controls reset signal to low for three clocks and release it to start a WRITE test followed by a READ register test.  https://alteraforum.com/forum/attachment.php?attachmentid=15162&stc=1   By checkign the modelsim waveform, I think the WRITE part is working because I can see the UART Tx serial output is the value that registed into "user_buffer_data" in writing sequence.  However, when I try to read the "status" register value the Master Template's actions is weird.   Since my Avalon-MM Master data width is set to 32bit, for my understanding the local address shift should be 4 bytes. According to Altera "Embedded Peripherals IP User Guide" table 67, if    I want to write data to "txdata" register, the address should be "Base Address + 4", where the "Base Address" in my project is 0x00000000. Because I can see the Tx serial line has correct output response, so I tried to read register "status", which's address is 0x00000000 + 8. But once I asserted "control_go" signal, the "control_done" is de-asserted and never goes high. Meanwhile I cannot get the asserted "user_data_available" and readout data successfully. https://alteraforum.com/forum/attachment.php?attachmentid=15163&stc=1   I found some of the threads in forum that if FIFO depth is set to 4 would generate the similar problem, however in my case this parameter is set to 32 already. Is there any part I miss or my understanding of using this Master Template is wrong?   Any suggestions will be welcome, thanks in advance!!!

[Altera_Forum]

Hi, how about your project? did you find a solution? I also want to use the Avalon MM Master Template the access the on-chip memory core in the Avalon bus from my self-defined component? Before the on-chip memory core connecting to the self-defined component it connected to a Avalon MM Master in a PCIe core and mapped the address to 0x02000000, and then connected the on-chip memory to the Master of the self-defined component and mapp to address 0x02000000 too, but what I read from the 0x02000000 in the self-defined component are all ZERO. Do you know what is the problem?