structural verilog with base library parts?

[Altera_Forum]

Hello, 

Is there a library of base parts (like a parameterized LAB for example?) that I can instantiate manually and maybe locate at a particular row,col address inside a device? Thanks, lefty

[Altera_Forum]

Designing with primitives is generally discouraged, as you are unlikely to do a better job than the synthesis tool. Is there a reason for wanting to use primitives? 

 there is this document from 11 years ago: https://www.altera.com/en_us/pdfs/literature/ug/ug_low_level.pdf and memories: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram_rom.pdf  If you want to lock them to specific locations, you need to use logiclock constraints. Guide here: http://www.alterawiki.com/uploads/6/61/tips_for_incrementalcompilation_logiclock.pdf  Basically, all of this is much much slower, and likely less efficient than writing HDL. Let alone being terrible for anyone else to read.

[Altera_Forum]

Thanks for fantastic information. My interest is just for learning purposes. From your advice I may not be able to place because I'm using the free version which has logiclock nobbled? 

   --- Quote Start ---  Designing with primitives is generally discouraged, as you are unlikely to do a better job than the synthesis tool. Is there a reason for wanting to use primitives?  there is this document from 11 years ago: https://www.altera.com/en_us/pdfs/literature/ug/ug_low_level.pdf and memories: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram_rom.pdf  If you want to lock them to specific locations, you need to use logiclock constraints. Guide here: http://www.alterawiki.com/uploads/6/61/tips_for_incrementalcompilation_logiclock.pdf  Basically, all of this is much much slower, and likely less efficient than writing HDL. Let alone being terrible for anyone else to read.  --- Quote End ---