PFL Mega Function: Setup time Issue

[Matt1]

hi all,

I am trying to implement Altera PFL IP (configuration is done for FPPx16) in MAX5 CPLD.

As per the datasheet i did all the constraining for the respective signals.

From the CPLD design compilation reports,the Fmax is shown only 94.21 MHz.

As per my requirement , PFL_CLK is set to 100Mhz.

The setup time issues are pointing to the internal signals in PFL IP.

Can anybody hep me in solving the issue,

Thanks in Advance.

[a_x_h_75]

From the user guide for the PFL:

"Any reference to the core clock speed of 100 MHz is only an example of the configuration time calculation and not a recommendation of the actual clock."

The PFL IP isn't necessarily designed to run at 100MHz. This depends entirely on the device in which you're trying to run it. It will run at 100MHz in the right device. However, it may well not run at 100MHz in the device you've chosen.

Cheers,

Alex

[GuaBin_N_Intel]

Yes, Alex is right. Refer to UG here https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf, 1.4.2.4, Table7, Fmax of IP core clock ​depends on which device and speed grade you are targeting. You can check the Fmax in slow corner from TQ report. There is no other optimization setting can be done for the internal path.

[Matt1]

Hello Alex & GNg,

thank you for the support.

Is it recommended to use some of the optimizing options which is available in Quartus tool to make it work close to 100Mhz?

@GNg, referring to ug_pfl.pdf, table 7 states that pfl_clk "Can be constrained up to the maximum frequency supported by the PFL IP core"'.

but I couldn't find any document which specifies the Fmax of PFL IP.

is there any document which give the reference of the Fmax ( pfl ip )for a series of cpld devices ?

what I meat is ,for example MAX V(part number:5Mxxxxxxxx) can support Fmax of  X Mhz .  

thanks

[GuaBin_N_Intel]

Have you tried to set IP GUI>Flash Programming>Speed? Also, set the fitter>optimization mode(performance) but it may have little help.

No, there is no UG stated Fmax of PFL IP in any device. It is soft IP and we have varies product range and families. What you can do is to run a compile with standalone PFL and see the Fmax you get.

[Matt1]

thanks for the reply.

I tried with Flash Programming>Speed, but the compilation failed due to resource limitations( as the device is 5M1270z).

[GuaBin_N_Intel]

This is resource limitation in your device part number. If you can't choose a larger max device, ​I think the option you have is to reduce the running core speed.

[Matt1]

hi GNg,

I solved the timing issues which were reported by the Quartus by changing the seed value and Fitter settings in the tool.

now the tool reports Fmax as 100.2Mhz

Thanks for your support

[Matt1]

yes,you are correct.

For now frequency reduction is the only option.

Thanks for the support.