Avalon Memory Mapped read and write pipeline

[CBob1]

I need a clarification regarding AMM's pipeline capabilities.

Context:

The Note under the Section 3.5.4.1. "Pipelined Read Transfer with Variable Latency" specifies that if waitrequestAllowance is greater than 0, then the slave must assert waitrequest soon enough to prevent pipeline overflow. In the next Section, 3.5.4.2. "Pipelined Read Transfers with Fixed Latency", the last sentence specifies that if a write command is issued by the master and the slave cannot process it, then it should assert waitrequest in order to stall the write transfer until the slave read pipe is emptied. 

Problem:

The problem is when the slave has the waitrequestAllowance property set to be greater than 0(equal to the master's property value) AND it supports only pipelined reads. If a write command is issued while there are still remaining read transfers in the pipe the slave asserts waitrequest in order to stall the master as the protocol specifies. So, the master should wait until the slave read pipe is emptied but, as the master has the property waitrequestAllowance set to be greater than 0, the master would expect the slave to process the write transfer and it may take as good the response that is on the bus at that time, fact that would break the response order rule.

Solutions:

I have found two possible solutions for this problem: 

1) The master should be aware of the number of responses that it needs to receive from the slave, fact that would tell the master when the slave finished processing the read transactions from it's pipe. So, with some additional logic, I can ignore the waitrequestAllowance property and stall the master as long as it is needed. 

2) If a slave supports pipeline for read transfers, then it must support pipeline for write transfers also, just like in the Burst case.

Which of these solutions is the correct one?

[GuaBin_N_Intel]

​I assume you were thinking the implementation from slave perspective. Here are my point of views:

1) Write transfer during read pending in process.

Not sure you have read this context

"The Avalon-MM specification does not define the value of readdata in the event that a slave accepts a write transfer to the same address as a currently pending read transfer"  in the same section 3.5.4.2 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf. There is no definition how slave handles when in situation that both read and write transfer are using the same address. So, slave is recommended to stall the transfer and complete all of pending read before executing the write transfer.

2) As you are using WaitrequestAllowance properties, I don't think you can ignore the transfer from master. Refer to section 3.5.2,

"specifies the number of transfers an AvalonMM master can issue or an Avalon-MM slave must accept after the waitrequest signal is asserted", with this statement, you have to provide a buffer at slave side to process the transfer after while asserting the waitrequest at the same time.