Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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JTAG to Avalon Master - reset signals

skon
Novice
1,246 Views

Hello,

 

The JTAG to Avalon Master bridge has one input reset signal called:

"clk_reset"

And one output reset signal called:

"master_reset"

 

Question:

If I assert the "clk_reset" at the input - will the reset output ( master_reset ) activate as a result ?

1 Reply
JohnT_Intel
Employee
505 Views

Hi,

 

It won't provide reset output. You will need​ to performed "jtag_debug_reset_system " in System Console in order to for it to reset the system.

Reply