FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6343 Discussions

Using Serial Flash Loader IP and ASMI Parallel II IP (Error (176286): Found 2 SPI blocks in design ...)

zeahr
Beginner
1,639 Views

Hello,

 

I want to use ASMI Parallel II IP to access EPCQ device from logic through Avalon-MM interface, also I want to use Serial Flash Loader IP so that I can program the EPCQ using JTAG interface. But an error occurred during fitting. Below is the error message.

**********************************

Error (176286): Found 2 SPI blocks in design -- only one SPI block is allowed

**********************************

 

Device = Cyclone V GX

 

Serial Flash Loader IP setting:

Share ASMI interface with your design = OFF

 

ASMI Parallel II IP:

Device Type = EPCQ256

I/O Mode = QUAD

Disable dedicated Active Serial Interface = OFF

Enable SPI pins interface = OFF

Enable flash simulation model = ON

 

Thank You.

Best Regards,

Zeahr

 

0 Kudos
1 Solution
Nooraini_Y_Intel
Employee
817 Views

Hi Zeahr,

 

Both SFL IP and ASMI Parallel II IP require ASMI interface access and by having both IPs in the same design would cause conflict during design compilation as both IPs cannot access the ASMI block at the same time.  Thus the error message is expected as you cannot use together both IPs in the same project design.

 

However the SFL IP and the ASMI PARALLEL IP should have an option to share or disable dedicated Active Serial interface option where the signals can be exported to top level and allow users able to use them to interface with ASMI block externally.

 

In this case, you should be able to use the SFL IP which is utilizing the ASMI block by tuning ON the “Share ASMI interface in the design” check box. With the ALTASMI PARALLEL IP, you need to turn ON the "Disable dedicated Active Serial Interface" option. Then route the ASMI signals from the ASMI PARALLEL IP connecting to the SFL IP ASMI input/output ports. Hence both IPs should be able to share the single ASMI block within the SFL IP and the Quartus compilation should be able to complete without failure.

 

You can refer to respective options from the SFL IP and ASMI PARALLEL IP userguide: 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an370.pdf?wapkw=an370

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altasmi_parallel.pdf

 

Regards,

Nooraini  

 

View solution in original post

2 Replies
Nooraini_Y_Intel
Employee
818 Views

Hi Zeahr,

 

Both SFL IP and ASMI Parallel II IP require ASMI interface access and by having both IPs in the same design would cause conflict during design compilation as both IPs cannot access the ASMI block at the same time.  Thus the error message is expected as you cannot use together both IPs in the same project design.

 

However the SFL IP and the ASMI PARALLEL IP should have an option to share or disable dedicated Active Serial interface option where the signals can be exported to top level and allow users able to use them to interface with ASMI block externally.

 

In this case, you should be able to use the SFL IP which is utilizing the ASMI block by tuning ON the “Share ASMI interface in the design” check box. With the ALTASMI PARALLEL IP, you need to turn ON the "Disable dedicated Active Serial Interface" option. Then route the ASMI signals from the ASMI PARALLEL IP connecting to the SFL IP ASMI input/output ports. Hence both IPs should be able to share the single ASMI block within the SFL IP and the Quartus compilation should be able to complete without failure.

 

You can refer to respective options from the SFL IP and ASMI PARALLEL IP userguide: 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an370.pdf?wapkw=an370

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altasmi_parallel.pdf

 

Regards,

Nooraini  

 

zeahr
Beginner
817 Views

Hi Nooraini,

 

Thank you for your reply.

I followed your instruction and it worked,  Quartus compilation was able to complete without failure.

 

Than you.

 

Best Regards,

Zeahr

 

0 Kudos
Reply