I have a design with an async external bus. I simply want to constrain the outputs so that they have a known delay relative to the driving clock of 25 MHz (or really anything known). I compiled the design withou8t constraints to look at the path delays on the outputs, then added constraints (set_max_delay, set_min_delay) such that the unconstrained design fit within the new constraints. There is a clock skew included (~-7 ns) that I don't understand what the tool is doing but apparently needs to be included in the delay, plus a 3-6 ns data delay. I set the max and min delay to 16 and 9 respectively which Timequest was perfectly happy with, no timing failures. No problem right? Well, when I rebuilt, Quartus added about 15ns to the data delay breaking the timing. What gives? It seems like there should be a simple solution (no I can't use fast registers). I also need to do something for the inputs. All help is appreciated.
