System Verilog Pass typedef struct packed between modules Error (12002): Port "X" does not exist in macrofunction "Y"

[Ken_I_Intel]

Hi,  I started to use typedef struct packed in my simulation no problems.  However when I try to pass compile the and pass a struct it gives an error message.  I just assumed I could pass a struct as a parameter.  My workaround is to pass it as a wire array and then reassign as a struct.

What is the correct way to do this? See attached code which has simple module called foo.

[Ken_I_Intel]

I'm using Quartus 18.0 standard edition.  My device target is ​MAX10.

[Ken_I_Intel]

Hi,

I think I found why I get 12002 error, and also I can pass structures as parameters in Quartus without having to hack my code back to array of wires. Quartus has bugs. There 1st issue is that once I see the error it remain even after making changes which will make it pass, I have to delete all temporary files and restart Quartus. The 2nd issue is that if the project uses sources files in a diffeent directory than the project files, quartus will generate the 12002 error if the library search feature is used. If every individual system verilog file is specified as a source files AND all the temporary files are deleted, then restarting Quartus will compile without error. Once it is passing, I can also revert the project settings to failing case and it will continue to pass.

I will escalate the issue as a Quartus BUG.

[GuaBin_N_Intel]

​I compiled your same HDL coding without any issue in Quartus Standard version18.1. Also, I tried to duplicate the 2nd issue you had but not succeed. It could compile even the source file put at different place than its project directory.

*******************

typedef struct packed

{

 logic a;

 logic b;

} t_ab;

endpackage

import types_package::*;

module foo (

 input sys_clk,

 input t_ab test_ab,

 output foo_out

);

reg foo_out_r;

assign foo_out = foo_out_r;

always@(posedge sys_clk)

 foo_out_r <= test_ab.a & test_ab.b;

endmodule

module struct_test (

 input sys_clk,

 input top_a,top_b,

 output wire test_out

);

t_ab test;

assign test.a = top_a;

assign test.b = top_b;

foo foo1(

 .sys_clk (sys_clk),

 .test_ab(test),

 .foo_out(test_out)

);

endmodule 

****************

[Ken_I_Intel]

Hi.,

Fyi I filed a support ticket already, but I probably was not specific enough in the forum. The way to generate this error is requires specific set of requirements. The error happens if:

• the project is setup in separate folder from the verilog source files
• AND the project settings to use Library path based search feature to find foo.sv rather than specify the file foo.sv in files setting
• AND all Quartus temporary files are deleted. (DB/INCREMENTAL_DB)

Attached is a zip with the entire demo project which will produce the error.

Once the error is occurs, it can be fixed by adding the file foo.sv to project. However the DB/INCRREMENTAL_DB/OUTPUT_FILES folders must be deleted otherwise the error continues. IE even if the fix is in place Quartus continues to fail. 

So, Quartus must be closed, then it possible to delete ALL Quartus generated folders like DB/INCREMENTAL_DB/OUTPUTFILES, and then restart and recompile, it will compile without error.

Once it passed, the error condition can be put back into QSF by removing the foo.sv files and using the search path feature Quarys will continue to compile without any errors. But deleting the temp folder again, restarting quartus will then cuase the compile error to reoccur. 

This issue was very annoying because it shows a conditional compile problem.  As such I think Quartus needs a clean build / FULL REBUILD button like a c++ IDE would have because it clearly not doing a good job here.

[jke]

The issue still exists in Quartus version 20.1.0 and version 21.1.0.

I'm facing the same issue with my project. Very annoying! 

I can reproduce this with the included project. Also the workaround seems to work, unfortunately not for my project.