Using HLS to target the FPGA from the Host(PowerPC)

[NSuku1]

Hi all,

I have a software running on the Power PC and I need to offload some mathematical tasks to the FPGA. I would like to know what are the appropriate tools for the software developer to use.

• Should I use Open cl pragmas in the software running on the host to just offload some functions to the FPGA?
• Separate the mathematical tasks and develop it using HLS to target the FPGA? If so, how can I interface it with the PowerPC through Serial Rapid IO?
• Can I program in C using HLS to target the FPGA?

Host: PowerPC

Interface: Serial Rapid IO

FPGA: Arria 10 devkit

Thanks in advance!

Kindly help me in finding the right tool to get started with the implementation.

Thanks,

Nivetha

[Kenny_Tan]

​You can use either HLS or Open Cl. Open CL are mostly target for software engineer while HLS are target for hardware engineers.

You refer to https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html

https://www.intel.com/content/www/us/en/software/programmable/sdk-for-opencl/overview.html

Thanks

[HRZ]

It would probably be easier to use OpenCL in your case since the PCI-E and DDR IP cores are pre-configured and provided in the BSP and a PCI-E driver is also provided to allow communication between the host and the FPGA. Furthermore, controlling interactions between the host and the FPGA is relatively easy using the basic functions provided by the OpenCL standard. With HLS, however, you can only compile parts of your C code into an HDL module, and then you will have to manually insert it into a complete HDL projects with all interfaces created/instantiated and managed by you.

[NSuku1]

Hi!

Thanks for the reply. I am using Serial Rapid IO as interface. So I cannot use the PCI-E IP cores.