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In PD I don't enable AER, but when the core is built and the FPGA is tested, the normal Linux lspci indicates that AER is enabled. In the non-SR-IOV core (just turning SR-IOV off), with AER not enabled, it does not show up in the PCIe config-space. Why?
Added edit: FYI - this is a version 18.0 pcie_a10_hip core.
Update: 12/04/18 - I was looking into a few of my questions further, some thoughts:
Also, and discussed on another post, I see in documentation an implication that with SR-IOV enabled the AER capability is always in the config space (I have not checked whether or not the "Enable Advanced Error Reporting" configuration (on/off) affects whether it indicates enabled (supported) or not. Is this observation true?
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Hi,
When you enable SR_IOV, the ARI support is enabled thus enabling AER capability (although not selected in the IP GUI).
Please check my reply for the following question:
Question:
Also, and discussed on another post, I see in documentation an implication that with SR-IOV enabled the AER capability is always in the config space (I have not checked whether or not the "Enable Advanced Error Reporting" configuration (on/off) affects whether it indicates enabled (supported) or not. Is this observation true?
Answer:
I cannot confirm if your observation is true as I never tried reading back AER errors with SR-IOV by unchecking "Enabled Advanced Error Reporting"
Since ARI is enabled with SR-IOV enabled, the AER Enhanced Capability Registers are available to indicate AER is available. However, to ensure the Configuration Space Registers are available please "Enable Advanced Error reporting".
Regards,
Nathan
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