coreboot hangs at post code 19 on Bayley Bay

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coreboot hangs at post code 19 on Bayley Bay

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Hi all,

When I try coreboot on Bayley Bay platform along with fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015), it is getting hang at post code 19.

Also I tried with debug version fsp (BAYTRAIL_FSP_GOLD_004_22-MAY-2015_DEBUG) , it still at that point and below is the debug log.

I have flashed the last 2 MB region with coreboot image upon 8 MB vendor bios.

coreboot gives the control to FSP binary service routine(FspInitApi) and it is getting hang when trying to do PCH initialize(PchMiscInit) inside FSP part code.

POST 19 code info : EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_CLOCK_PEI_INIT_ENTRY ==> Clock Init PEIM Entry

I have not seen the clock related setting available when customizing fsp binary using BCT.

I tried to disable south cluster component such as EMMC,HSUART,SATA and SIO using BCT , it didn't help me.

Can anyone please help me provide some inputs such as related below to proceed further debugging on it ?

1. Any other setting we can try out using BCT

2. About devices configuration to be initialized byPchMiscInit function.

3. Anything need to be cared/double checked from coreboot side in order to giving control to FspInitApi function.

4. Does pch straps settings may cause this since I am using upper 6 MB region flash data which is from vendor bios.

4. Please suggest anything on it.

Thanks in advance,

Kathappan

<<<<<<<<<<<< Start >>>>>>>>>>>>>>>

coreboot-coreboot-unknown Thu May 12 08:04:42 UTC 2016 romstage starting...

RTC Init

POST: 0x44

POST: 0x47

POST: 0x48

Starting the Intel FSP (early_init)

PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x44000

prev_sleep_state = S5

Configure Default UPD Data

PcdMrcInitSPDAddr1: 0xa0 (default)

PcdMrcInitSPDAddr2: 0xa2 (default)

PcdSataMode: 0x01 (set)

PcdLpssSioEnablePciMode: 0x01 (default)

PcdMrcInitMmioSize: 0x800 (default)

PcdIgdDvmt50PreAlloc: 0x02 (default)

PcdApertureSize: 0x02 (default)

PcdGttSize: 0x02 (default)

SerialDebugPortAddress: 0x3f8 (default)

SerialDebugPortType: 0x01 (default)

PcdMrcDebugMsg: 0x01 (default)

PcdSccEnablePciMode: 0x01 (default)

IgdRenderStandby: 0x00 (default)

TxeUmaEnable: 0x00 (default)

PcdOsSelection: 0x04 (default)

PcdEMMC45DDR50Enabled: 0x01 (default)

PcdEMMC45HS200Enabled: 0x00 (default)

PcdEMMC45RetuneTimerValue: 0x08 (default)

PcdEnableIgd: 0x01 (default)

AutoSelfRefreshEnable: 0x00 (default)

APTaskTimeoutCnt: 0x00 (default)

GTT Size: 2 MB

Tseg Size: 8 MB

Aperture Size: 256 MB

IGD Memory Size: 64 MB

MMIO Size: 2048 MB

MIPI/ISP: Disabled

Sdio: Enabled

Sdcard: Enabled

SATA: Enabled

SIO Dma 0: Enabled

SIO I2C0: Enabled

SIO I2C1: Enabled

SIO I2C2: Enabled

SIO I2C3: Enabled

SIO I2C4: Enabled

SIO I2C5: Enabled

SIO I2C6: Enabled

Azalia: Enabled

SIO Dma1: Enabled

Pwm0: Enabled

Pwm1: Enabled

Hsuart0: Enabled

Hsuart1: Enabled

Spi: Enabled

Lpe: Disabled

eMMC Mode: eMMC 4.5

SATA Mode: AHCI

Xhci: Enabled

POST: 0x92

============= PEIM FSP (VLYVIEW0 0x00000304) =============

Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3

Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A

The 0th FV start address is 0x000FFFE0400, size is 0x00017C00, handle is 0x0

Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389

Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480

Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1

Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39

Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: FFFE0FD4

The 1th FV start address is 0x000FFFB0000, size is 0x0002F400, handle is 0xFFFB0000

Install PPI: A55D6970-1306-440C-8C72-8F51FAFB2926

PcdMrcInitTsegSize = 8

PcdMrcInitMmioSize = 800

PcdMrcInitSPDAddr1 = A0

PcdMrcInitSPDAddr2 = A2

Setting BootMode to 0

Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56

About to call MrcInit();

BayleyBay Platform Type

RID = 0x11.

Reg_EFF_DualCH_EN = 0x40030040.

CurrentMrcData.BootMode = 4

C1.D0: SPD not present.

Configuring Memory Start...

START_RMT:

RxDqLeft RxDqRight RxVLow RxVHigh TxDqLeft TxDqRight CmdLeft CmdRight

------------------------------------------------------------------------------------------------

Channel 0 Rank 0 -22 21 -21 19 -25 26 0 0

STOP_RMT:

CMD module is per channel only and without Rank differentiation

Configuring Memory End

UpperTotalMemory = 0x80000000

dBMBOUND = 0x80000000

dBMBOUNDHI = 0x80000000

dGFXBase ...

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18 Replies

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Hello Kathappan ,

Thank you for contacting the Intel Embedded Community.

We have received your consultations and we are working to answer them as soon as possible.

Thanks in advance for your patience and understanding.

Best Regards,

Carlos_A.

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Hello Kathappan

Could you please clarify the following statement:

Kathappan E wrote:

I have flashed the last 2 MB region with coreboot image upon 8 MB vendor bios.

Why are you mixing to bios binaries on a single chip?

Is there any issue if you use the original BIOS of the Bayley Bay?

Are you including TXE firmware in your platform?

I will be waiting for your feedback.

Best Regards,

Adolfo Sanchez

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Hi Adolfo,

Sorry for the delay. Before going to answer your questions, I share some info.

First I am new to learn about coreboot source. So, I choose the FSP binary to build coreboot and make a trial on Intel board. I have one Bayley Bay custom board (not a CRB) which is based Atom E3825 and D0 stepping SoC.

Why are you mixing to bios binaries on a single chip?

Actually , I tried with 2 MB coreboot and it is not even getting detectedand I meant it is hang at postcode 00.

After some research I come to know it is required TXE and flash descriptor to proceed but don't have TXE and descriptor binary to add and make 8 MB flash image along with coreboot. But I have vendor BIOS (8 MB) which has TXE and flash descriptor. Hence, I updated coreboot image upon it to boot it.

Is there any issue if you use the original BIOS of the Bayley Bay?

No issues faced. It is booting fine.

Are you including TXE firmware in your platform?

I believe, it has been included since I am using upper 6 MB from vendor bios.

Can you please help me to provide inputs to proceed further ?

Thanks,

Kathappan

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Hello Kathappan

This is not the proper way to merge your BIOS with the coreboot.rom image.

Here are the options that you could try

1) You can try is using the Intel FPT tool to replace the BIOS section of the SPI with your own .rom image (you need to make sure to unlock your BIOS before performing this step)

2) You can download the Intel TXE and create your own .bin file using the FITC tool, the disadvantage of this method is that you will need to configure the description region and the TXE by yourself.

3)This is similar to the first option the difference is that you should ask your BIOS vendor if they have a tool to update the BIOS (some vendors provide those tools).

The FITC and FPT tools come together with the TXE image that can be downloaded here: https://edc.intel.com/Link.aspx?id=9982 https://edc.intel.com/Link.aspx?id=9982

But you need to have a Privilege Account to download it, you can apply here for privilege access: http://www.intel.com/content/www/us/en/forms/design/registration-privileged.html http://www.intel.com/content/www/us/en/forms/design/registration-privileged.html

Additionally what tool are you using to program the .rom image on your SPI?

Best Regards,

Adolfo.

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Hello Kathappan

I have and additional option that might be useful for your case, the only thing that you need is to have the original .bin file from your BIOS vendor.

You use the ifdtool that comes included with the coreboot package to extract the file descriptor and the txe binaries from your bios .bin file, then you merge them in your coreboot image.

You can find more information on the following link: http://wiki.minnowboard.org/Coreboot# Intel.C2.AE_Firmware_Support_Package_.28Intel.C2.AE_FSP.29 http://wiki.minnowboard.org/Coreboot# Intel.C2.AE_Firmware_Support_Package_.28Intel.C2.AE_FSP.29

On the section TXE and SPI descriptor.

Please note that the site is strictly for Minnowboard, you might need to rename the file me.bin instead of txe.bin depending on your coreboot version.

I hope this information is useful for your case.

Best Regards,

Adolfo Sanchez.

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Hi Adolfo,

Thanks for your comments and sorry for the late reply. Here is consolidated points form my side.

1) You can try is using the Intel FPT tool to replace the BIOS section of the SPI with your own .rom image (you need to make sure to unlock your BIOS before performing this step)

I will try to get FPT and check on it.

2) You can download the Intel TXE and create your own .bin file using the FITC tool, the disadvantage of this method is that you will need to configure the description region and the TXE by yourself.

I am checking to get privileged access.

3)This is similar to the first option the difference is that you should ask your BIOS vendor if they have a tool to update the BIOS (some vendors provide those tools).

As of now, I am unable to contact them and will try get it later.

Additionally what tool are you using to program the .rom image on your SPI?

I am using Dediprog SF100.

Extracting descriptor bins using ifdtool

I tried same to extract the Vendor BIOS image (8 MB) and I got the below map and binaries.

Flash Region 0 (Flash Descriptor): 00000000 - 00000fff

Flash Region 1 (BIOS): 00300000 - 007fffff

Flash Region 2 (Intel ME): 00001000 - 002fffff

Flash Region 3 (GbE): 00fff000 - 00000fff (unused)

Flash Region 4 (Platform Data): 00fff000 - 00000fff (unused)

flashregion_0_flashdescriptor.bin => renamed to descriptor.bin

flashregion_1_bios.bin

flashregion_2_intel_me.bin => renamed to me.bin

Have configured the same in menuconfig and build the 8 MB coreboot image

But still source is getting hang at same point (post code 0x19) => PchMiscInit() - Start inside the FSP code.

I am not sure that external factors (such asTXE/ME/Descriptor/coreboot) does cause it getting infinite loop(may be timeout) when device initialization (pcie). But I suspect it may due to FSP code. Also I tried latest FSP available in Intel site for bayleybay platform , it didn't help.

I would be more useful for me if you give more points.

Thanks a lot for your support,

Kathappan

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Hello Kathappan

Just for clarification:

1) Are you replacing all the SPI contents with the 8MB coreboot image or you are adding the image and the end of your original BIOS?

2) Are you adjusting the FSP image to your configuration using the BCT tool?

Best Regards,

Adolfo Sanchez.

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Hi Adolfo,

# 1) Initially I tried with adding 2 MB coreboot image at end of original bios (offset 600000 - 7fffff). Then I have tried with creating 8 MB coreboot image using extracted descriptor/me binaries from vendor bios (as you suggested ).

# 2) No, I have not changed anything on FSP using BCT. Only thing I did was configuring FSP loader address in KConfig from menuconfig as 0xfffc0000 and 0xfffb0000 for release and debug FSP binaries.

Thanks for your support,

Kathappan

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Hello Kathappan

You must make sure to use the BCT tool to adjust the options of the FSP so they match with the hardware of your board.

Please make sure to perform that process in case that any missmatch between the FSP default settings and your hardware board are causing your issue.

You can download the BCT tool here: http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html Intel® Firmware Support Package Preserves Frameworks

Best Regards,

Adolfo Sanchez

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Hi Adolfo,

I tried to change some items using BCT and it didn't help. I will check more to change the configuration using BCT and will let you know the status.

Thanks a lot for your support.

Thanks,

Kathappan

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Dear Adolf,

Link to download FITC and FPT tools is not working. Please provide the working link to download FITC and FPT tools.

Thanks

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Hello

I am working on fixing the link, sorry for the inconvenience that this might cause you.

Best Regards,

Adolfo Sanchez

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Hello SABARIVASA@ECIL

I have sent you an e-mail with additional instructions while we fix the issue with the link.

Best Regards,

Adolfo Sanchez

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Dear AdolfoS

Thanks.... I have got the tools....

I need one more document which i could not find on Intel website... kindly share me link for following file..

539374:Secure Boot Sample Implementation for Intel(R) Atom™ Processor E3800 Product Family README

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Hello Sabari

I am having some issues to locate the file, I will update you as soon as possible

Best Regards,

Adolfo Sanchez

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Hello Sabari

Just to let you know, that I am in the process of uploading the requested file to the EDC Library.

Best Regards,

Adolfo Sanchez

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Hello, am Bob new to coreboot ...have been trying to compile coreboot for Intel BAYTRAIL custom board following this https://minnowboard.org/tutorials/alternate-firmware https://minnowboard.org/tutorials/alternate-firmware tutorial ..have been having errors ..image not compiling properly please help

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Hello, bobraphtoneafwata:

Thank you for contacting Intel Embedded Community.

Reviewing your previous communication, your problem is related to a third design and a suggested configuration provided by the developer of this project. Due to these facts, we suggest you address your questions as a reference at the following websites:

https://minnowboard.org/community https://minnowboard.org/community

http://lists.elinux.org/mailman/listinfo/elinux-minnowboard elinux-MinnowBoard Info Page

https://www.coreboot.org/consulting.html https://www.coreboot.org/consulting.html

We hope that this information may help you.

Best regards,

Carlos_A.

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