Change Host Control2 Register APL GP

[FCama1]

Hello,

From document number 557556 (EDS vol 2) there is at Offset 3Eh Host Control2 Register (hostcontrol2), I would like to change hostctrl2_driverstrength does someone has the configuration and how to apply to a ABL build?

Regards,

Francesco

[CarlosAM_INTEL]

Hello, fcamarda:

Thank you for contacting Intel Embedded Community.

The driver strength select field in Host Control 2 Register (bit 9 [hostctrl2_driverstrength_bit2]) defaults to "0" (3.3V mode drive strength [3.3V signaling]). Setting this bit to "1" selects the 1.8V mode drive strength [1.8V signaling].

The driver strength depends on the setting of bit 15 (hostctrl2_presetvalueenable). If Preset Value Enable = 0, the driver strength is set by the host driver. If Preset Value Enable = 1, the driver strength is automatically set to the values specified in the Capabilities Register (capabilities)—Offset 40h (refer also to Capabilities Register (capabilities)—Offset 40h).

You can confirm this information in sections 22.5.29 and 22.5.30, on pages from 4511 to 4515 of the https://edc.intel.com/Link.aspx?id=14201 Apollo Lake SoC External Design Specification (EDS) Volume 2 of 3 document # 557556 that you have mentioned.

We hope that this information may help you.

Best regards,

Carlos_A.

[FCama1]

Hello Carlos_A,

thank you for the details.

Now could you please tell me which is the file I have to change to implement hostctrl2_presetvalueenable = 1 (instead of 0) ? Where can I find the Host Control 2 Register config?

And then use the Capabilities Register values that from my understanding came from the device (CAP) through the linux device driver ...

Regards,

fcamarda

[CarlosAM_INTEL]

Hello, fcamarda:

Thanks for your update.

In order to be on the same page, could you please tell me what Linux version and variant you are using for the cited propose?

Waiting for your clarification.

Best regards,

Carlos_A.

[FCama1]

Hello Carlos_A,

I am using the:

linux-apl:

meta-ias-gr-mrb-bsp 4.1.27

to build it I followed the guide Document Number: 567191-1.42 from the gp_bsp_ww23.5_ec31_pf_rc1.zip package for APL soc and GP board.

Regards,

fcamarda

[CarlosAM_INTEL]

Hello, fcamarda:

Thanks for your update.

In order to help you as a reference please address your last questions to the channels listed at the http://git.yoctoproject.org/cgit/cgit.cgi/meta-intel/commit/ meta-intel - Layer containing Intel hardware support metadata website.

We hope that this information may help you.

Best regards,

Carlos_A.

[FCama1]

Hello Carlos_A,

no feedback from meta-intel... Is there an other way to have this information?

Thanks & Regards,

fcamarda

[CarlosAM_INTEL]

Hello, fcamarda:

Thanks for your reply.

We suggest you address your consultations related to this topic at the channels listed at the following website as a reference:

https://lists.yoctoproject.org/listinfo/meta-intel https://lists.yoctoproject.org/listinfo/meta-intel

We hope that this information may help you.

Best regards,

Carlos_A.

[Jingyu_Z_Intel]

Hi Carlos,

Could you also provide the decoding of the bit[5:4] hostctrl2_driverstrength value from 0x0 to 0x3? How it is mapped to the output impedance?

Thanks!

[CarlosAM_INTEL]

Hello, Maxzhou:

Thank you for contacting Intel Embedded Community.

In order to help you, we will contact you via email.

Best regards,

Carlos_A.