Cannot program an I211 controller

JDubo5 · ‎10-24-2017

Hello there,

I'm having issues flashing the I211 controller with the eepromARMtool. I've double checked both the HW and SW settings of my design and everything appears correct. Whenever I tried to flash the board using the eepromARMtool I always get the same results at the end: "Flash wordsize reg val: 15 register ffffffff". Also the dump of the nvm content is always blank. So I've 3 questions for you:

1) Is it ok that "Memory Type Present" is shown as "INVM+FLASH" when I run the eepromARMtool utility with no arguments?

root@board:/opt/tool# ./eepromARMtool

Intel(R) Eeprom ARM Tool ARM OTP Programming Tool

Provided under the terms of a CNDA. Do Not Distribute.

NIC BUS DEV FUN Silicon Memory Type Present

=== === === === ===== ======================

1 1 0 0 I211 INVM+FLASH

2) Is it ok to get "Flash wordsize reg val: 15 register ffffffff" when I attempt to flash the board? I'm using "./eepromARMtool -nic=1 -write -f=/opt/tool/hex_files/I211_Invm_NoAPM_v0.6.HEX" and "./eepromARMtool -nic=1 -f=/opt/tool/hex_files/I211_Invm_NoAPM_v0.6.HEX" commands

root@board:/opt/tool# ./eepromARMtool -nic=1 -write -f=/opt/tool/hex_files/I211_Invm_NoAPM_v0.6.HEX

Intel(R) Eeprom ARM Tool NVM/OTP Programming Tool

Provided under the terms of a CNDA. Do Not Distribute.

Version 0.6.7

Flash wordsize reg val: 15 register ffffffff

3) Can you double check the output from lspci -vvv to verify if everything looks correct?

01:00.0 Ethernet controller: Intel Corporation Device 1532 (rev 03)

Subsystem: Intel Corporation Device 0000

Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR-

Interrupt: pin A routed to IRQ 130

Region 0: [virtual] Memory at 13000000 (32-bit, non-prefetchable) [size=128K]

Region 2: I/O ports at 1000 [size=32]

Region 3: [virtual] Memory at 13020000 (32-bit, non-prefetchable) [size=16K]

Capabilities: [40] Power Management version 3

Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)

Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-

Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+

Address: 0000000000000000 Data: 0000

Masking: 00000000 Pending: 00000000

Capabilities: [70] MSI-X: Enable- Count=5 Masked-

Vector table: BAR=3 offset=00000000

PBA: BAR=3 offset=00002000

Capabilities: [a0] Express (v2) Endpoint, MSI 00

DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us

ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+

DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-

RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-

MaxPayload 128 bytes, MaxReadReq 512 bytes

DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-

LnkCap: Port # 0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <16us

ClockPM- Surprise- LLActRep- BwNot-

LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-

ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR+, OBFF Via WAKE#

DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled

LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-

Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-

Compliance De-emphasis: -6dB

LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-

EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-

Capabilities: [100 v2] Advanced Error Reporting

UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-

UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-

CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-

CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+

AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-

Capabilities: [140 v1] Device Serial Number 00-a0-c9-ff-ff-00-00-00

Capabilities: [1a0 v1] Transaction Processing Hints

Device specific mode supported

Steering table in TPH capability structure

Capabilities: [1c0 v1] Latency Tolerance Reporting

Max snoop latency: 0ns

Max no snoop latency: 0ns

Thanks,

Novo.

CarlosAM_INTEL · ‎10-24-2017

Hello, jsdmichaud1 :

Thank you for contacting Intel Embedded Community.

In order to be on the same page, could you please tell us if your design fulfills the requirements stated as answers to the questions 2.24, 2.14, and 2.15, on pages 9 and 8 of the https://www.intel.com/content/dam/www/public/us/en/documents/faqs/ethernet-controller-i210-i211-faq.pdf Intel(R) Ethernet Controller I210/I211 Frequently Asked Questions (FAQs) document # 335346?

Please let us know the information that should answer the previous question.

Waiting for your reply.

Best regards,

Carlos_A.