Could not find the answer for the question:
How is memory access organised in Nehalem 5500/5600 series.
Well, the documentation says that the processors have 3 memory channels, each supporting up to 3 memory slot, with up 8-rank memory modules (with up to 48 ranks in total).
Also you have 1333MHz memory speed with up to 8 total ranks, 1066MHz with up to 24 total ranks, 800MHz with more and max 1066MHz with 8GB / 800MHz with 16GB modules
And that is tho whole info I could find. But this is not adequate!
Sample question - now there are 2GB 4-ranks modules and 4 rank 16GB modules - will both run at 800MHz if 12 modules are intalled?
Really I'd like to get the answer for the following - which way the memory is adressed and reached.
Is it spanned across banks/ranks (bank1 rank1 - bank2 rank1 - bank3 rank1 - bank1 rank2 - bank2 rank2 ...) or some other way?
When it is possible to read/write the next rank of the bank (after 7-9 clocks or after 20-22 clocks or more)?
I want to understand the dependance of the amount of the memory installed on the real memory speed.
In workstation applications the big RAM-drive is a great help, but if it decreases system number-crunching performance, may be it ai more wise to have it on an axialary server?
