Intel I7 Cache

[idata]

I´m looking for the knowledge of cache system organization on I7 processors. If anybody can help me I should like to know:

The type of organization of the different levels of cache, i.e., if they are associative, direct mapped or N set associative.The answer in clock cycles of a Cache reading. I suppose that level 1 will be read in 1 clock cycle. And what about cache Level 2 and Level 3? Is the memory interface which generates the Wait State if there is a cache miss on Level 1 or is Level 1 by itself?Are the different levels of cache inclusive or exclusive?The policy of writing is Write through or write back?

Why I7 and these questions?

I7 because it is my processor.

These questions because I'm investigating about the logical interaction between cache and main memory and looking for the logical organisation of each one. I should like to see in a real situation the confirmation or not of my conclusions about cache memory.

[idata · Accepted solution]

Try the product support page of I7 processor.

[idata]

I have to keep my question. I thank thr Boyett's answer but I was very explicit in my question. I asked Who is Noah. I do perfectly know that if I read the Bible I will find the answer. Just not so sure about the datasheet of I7. The question is that I have no time to do it for the moment. So, please i ask a concret answer to my questions if possible and if someone is aware to do it.

[idata]

No. I touched the improper key. This question is not answered.

[idata]

I am sorry to say that Intel design do not follow Level 3 Cache it is the AMD design to have Level 3 Cache so will be the case of I7.

Where from i can get the seek time and fault times for the Intel Processors Cache