What is the Memory to L3 Cache mapping function for Nehalem Architecture (Xeon X3430)

[MGodf]

Hello Community,

I am a a researcher working with the mappings from physical memory to the shared L3 cache on a Xeon X3430 processor. We purchased the X3430 specifically because the Nehalem architecture (unlike Sandy Bridge) has no mention of sectioning (slicing) the cache and would imply a direct mapping from memory addresses to cache lines.

Our experiments, and some new-found documentation, implies that this may not be the case. Images of the processor, as well as minor mentions in some documentation, suggests that the L3 may be sectioned, which would imply some sort of novel mapping.

Would anyone have any information regarding how the L3 cache in Nehalem processors would map memory? Sandy Bridge is documented as using a simple hash function (although it does not specify the function). So long as we know how to predict which cache lines are mapped to which memory addresses (and vice versa) we can incorporate it into our experiments and get everything back on track.

Alternatively, if anyone can put me in direct contact with an Intel Engineer (I have had no luck through conventional channels) it would be much appreciated.

Thanks for the help.

-Michael

[Silvia_L_Intel1]

Hello Michael,

Let me try to find some information for you. I will keep you posted.

Regards,

Silvia L

[MGodf]

Thanks Silvia,

I will keep following any leads I find, but any information you can provide me would likely be the most useful.

-Michael

[Silvia_L_Intel1]

Michael,

According to the research we did there is no way to map the L3 cache memory in a Xeon processor.

Regards,

Sylvia L

[MGodf]

Can you provide me with more information or context regarding this answer?

To clarify, what I specifically need is a way to predict a subset of where each memory address may go. It does not have to be an exact line. The associative set would be ideal.

I am aware that you would not be able to get a one to one mapping of memory addresses to cache lines, but I would assume that you should at least be able to map a memory address to an associative set (if the cache has 16-way associativity then you should be able to map a memory address to a subset of 16 possible lines). This has successfully been done with other processors. If not to an associative set, then I would still expect some level of prediction to be possible, as it serves no purpose that I know to make the cache hardware non-deterministic.

According to my research, mapping memory to cache lines is a relatively standardized technique, so if Xeon processors don't allow this sort of prediction then they must be doing something unique. If this is the case, could you elaborate on what features or changes disable this kind of prediction? If it can't be done on a Xeon I will need to acquire a new processor and I need to know what qualities to avoid.

Ideally, if you could specify an Intel processor that would work in this context, that would be great.

Thanks for your help,

-Michael