Cache Coherence Granularity

[bzhan16]

Hi all,

Empirically the cache line size of most processors is believed to be 64 Bytes. And it is indeed confirmed

in my Linux machine by checking out the file /proc/cpuinfo.

But my question is, what's the basic size of the cache coherence protocol inside the processor?

Supposing a MSI protocol, is it true that a single cache line is tagged as, say, "M" state, or, they

are tagged in a bigger granularity, such as 2 or 4 lines are packed together to be marked in the "M"

state? Because according to my experience, it seems that the Xeon(R) CPU E5-2650 processor

tags two cache lines together.

Thank you very much.

[Allan_J_Intel1]

Hi benlong,

The LLC operates on 64 byte cache lines. It can tag 2 lines together for efficiency in rare circumstances, but the basic architecture is 64 byte lines.

Thanks

Allan

[bzhan16]

Hi Allan,

Then what's the implication by "in rare circumstances", does it mean that the LLC can work in two modes, or that

most processors tag 64 Bytes but rare processors do 128 Bytes?

And what about the L1 and L2 cache ?

Thank you very much.

Benlong

[Allan_J_Intel1]

Hi benlong,

It means that in some circumstances, the processor will tag 2 lines at once for efficiency. It is not CPU model specific and is not common.

L1 and L2 always work at 64 byte.

Allan