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Why did I get an 1 on a reserved bit of IA32_MTRRCAP register?

XWang41
Beginner
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I'm trying to do some memory management on xen-4.5.0, and get confused with something about MTRR(Memory-type-range-register). While I was trying to get the value of IA32_MTRRCAP register, I got value 1d0a.

However, in the Intel manual released in December 2016, bits 12-63 of IA32_MTRRCAP register are all marked reserved, while I got an 1 on bit 12. Why?

Meanwhile, when I was trying to read memory information from MTRRs, I could not find most of memory addresses in them.

I've tried these on several machines with Intel Skylake processors, and their situations are the same. But on machines with Intel Haswell processors, the value of IA32_MTRRCAP has nothing strange, I can also read all memory information from MTRRs.

Did the programming way of MTRRs change in Skylake? I can only guess in this way.

Thanks.

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idata
Employee
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Hello gcrow,

 

 

Thank you for contacting Intel Communities.

 

 

Can you please provide the following information to better assist you?
  • The model number for the tested Haswell & Skylake processors.
  • URL that leads to the document in question: "the Intel manual released in December 2016, bits 12-63 of IA32_MTRRCAP"
  • Steps to replicate the issue.
Hope to hear from you soon.

 

 

Regards,

 

Juan Carlos
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XWang41
Beginner
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The model number for Haswell is Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz, for Skylake is Intel(R) Xeon(R) CPU E3-1230 v5 @ 3.40GHz.

The URL of the document is https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf , Figure 11.5, page 3092. In this figure, bits 12-63 are reserved.

The code for getting value of IA32_MTRRCAP and get memory info from MTRRs:

rdmsrl(MSR_MTRRdefType, msr_deftype);

sprintk("MTRRdefType=%lx\n", msr_deftype);

rdmsrl(MSR_MTRRcap, msr_cap);

sprintk("MTRRcap=%lx\n", msr_cap);

vcnt = (int)(msr_cap & MTRR_VCNT_MASK);

for (idx = 0; idx < vcnt; idx += 1) {

rdmsrl(MSR_IA32_MTRR_PHYSBASE(idx), base);

rdmsrl(MSR_IA32_MTRR_PHYSMASK(idx), mask);

if (!(mask & MTRR_VRRP_MASK_MASK)) continue;

start_mfn = base >> 12;

//num_mfn: amount of pages

num_mfn = (~(mask >> 12) & ((1UL << (phys_addr_size - 12)) - 1)) + 1;

mem_type = base & 0xff;

sprintk("===MTTR base=%lx mask=%lx start=%lx num_mfn=%d type=%d\n",

base, mask, start_mfn, (int)num_mfn, mem_type);

}

And the output on Haswell:

(XEN) [0] vmx.c:806 MTRRdefType=c00

(XEN) [0] vmx.c:811 MTRRcap=d0a

(XEN) [0] vmx.c:820 ept table root va=ffff83081e82e000

(XEN) [0] vmx.c:855 ===MTTR base=6 mask=7800000800 start=0 num_mfn=8388608 type=6

(XEN) [0] vmx.c:855 ===MTTR base=800000006 mask=7fc0000800 start=800000 num_mfn=262144 type=6

(XEN) [0] vmx.c:855 ===MTTR base=c0000000 mask=7fc0000800 start=c0000 num_mfn=262144 type=0

(XEN) [0] vmx.c:855 ===MTTR base=bc000000 mask=7ffc000800 start=bc000 num_mfn=16384 type=0

(XEN) [0] vmx.c:855 ===MTTR base=bb800000 mask=7fff800800 start=bb800 num_mfn=2048 type=0

(XEN) [0] vmx.c:855 ===MTTR base=83f800000 mask=7fff800800 start=83f800 num_mfn=2048 type=0

(XEN) [0] vmx.c:855 ===MTTR base=83f600000 mask=7fffe00800 start=83f600 num_mfn=512 type=0

Output on Skylake:

(XEN) [0] vmx.c:839 MTRRdefType=c06

(XEN) [0] vmx.c:844 MTRRcap=1d0a // got 1 on bit 12

(XEN) [0] vmx.c:855 ept table root va=ffff8304588ef000

(XEN) [0] vmx.c:892 ===MTTR base=c0000000 mask=7fc0000800 start=c0000 num_mfn=262144 type=0

(XEN) [0] vmx.c:892 ===MTTR base=a0000000 mask=7fe0000800 start=a0000 num_mfn=131072 type=0

(XEN) [0] vmx.c:892 ===MTTR base=90000000 mask=7ff0000800 start=90000 num_mfn=65536 type=0

Where I cannot find most of memory on Skylake, and all found memory is UC type.

Thank you very much!

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idata
Employee
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Hello gcrow,

 

 

Thank you for the information.

 

 

I will do some research on this and will update this thread once I have further information.

 

 

Regards,

 

Juan Carlos
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XWang41
Beginner
618 Views

Thank you very much.

Hope to hear from you soon.

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idata
Employee
618 Views

Hello gcrow,

 

 

Thank you for waiting

 

 

After some research, the best option is to post your question in the https://software.intel.com/en-us/forum# Intel® Developer Zone Forums.

 

 

Regards,

 

Juan Carlos
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