Detection of CPLD successfully configured.

[KURK123]

Hi All,

I am working on a board with CPLD and three other FPGAs. I am able to configure the CPLD using it's pof file. My question is, is there a way to indicate that the CPLD is configured correctly? I have a pin that is supposed to go high when the configuration is complete. But I do not know how to make this pin go high once the configuration is successful.

Thank you in advance.

[Vicky1]

Hi,

I presume that, you have done pin assignment(Assignments->pin planner) for your design & then configured the CPLD using .pof file.

Now try to operate the appropriate slide switch/push button as you have assigned it in pin planner & check the status of appropriate LED for output/result.

Refer the below link for the reference,

https://www.youtube.com/watch?v=VzRLirqt_wI

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[KURK123]

Thank you for your reply.

Yes I have done the pin mapping correctly and configured the CPLD using the .pof file. It is successful too.

I have a custom board and I have not connected the push button/slide switch to the indicator pin. Though it is connected to the LED.

Shall I write some lines of VHDL code to indicate the CPLD_DONE pin should go high once the the configuration is complete?

I don't think so but please let me know if I am missing anything.

Thank you

[Vicky1 · Accepted solution]

Hi,

In case of custom board, I believe it should have some test points/nodes where you can make use of probes for multi-meter or Oscilloscope.

you can make a use of simple D Flipflop code for checking the status of particular pin of CPLD.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

[KURK123]

Thank you Vicky.

I have used the multimeter probes and it does show that the pin goes high once the configuration to the CPLD is complete.

I implemented the D-Flipflop code to check. And this convinces me.I wonder why it didn't strike me earlier.

Thank you once again.