FPGA, SoC, And CPLD Boards And Kits
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Status register after warm reset isn't set

MBach3
Beginner
‎12-12-2018 10:07 AM
1,460 Views

Hi

I'm using a custom board with a cyclone v fpga. The bare metal application, enables the watchdog. According the documentation should have a bit setted in rstmgr.stat field. I read them after a wd is happen, but the register are 0.

 

Do anyone have a successful configered watchdog and can explain a working solution.

 

Regards

Tinu

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Ahmed_H_Intel1
Employee
‎12-14-2018 02:52 AM
289 Views

Hi,

To learn about the Bare Metal please check the following:

1- Document to learn

https://www.intel.com/content/www/us/en/programmable/documentation/lro1424280108409.html

 

2- How to Video

https://www.youtube.com/watch?v=GHuM2mBlLxc

 

3- Examples for CycloneVSoC

https://github.com/robertofem/CycloneVSoC-examples

 

Regards,

Ahmed

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