LL 10G Eth MAC AVST TX Interface Timing Diagram

[JShel4]

10G LL Ethernet MAC: Newbie question on the timing diagram for the AVST TX Interface. In TX introduction, the user guide says: "The MAC TX receives the client payload data with the destination and source

addresses, and appends various control fields depending on the MAC configuration." And shows the Frame concept in a picture on page 37-38.

Then in the timing diagram (on page 43), the user guide is showing relation between AVST TX data and XGMII data interfaces.

Question:

• IF I want to send packets over a point-to-point connection between FPGA board and a desktop PC (connected via SFP+ cable), do I have to always include the destination addr, source addr. and length fields (i.e. 116bits) along with the Payload?
• AND how does the MAC know if I am including the optional Preamble, pad and crc bits? is there a control register that I need to update/write into?
• ALSO, how do I set the MAC address on the FPGA side (which will be the source address in the frame on page 38 of user guide)?

Thank You in advance to anyone who helps!

User Guide is the "Low Latency Ethernet 10G MAC

Intel ® FPGA IP User Guide"

[Deshi_Intel]

Hi JShel4,

Short answer to your question 1 is YES.

I presume you are using Intel Arria 10 FPGA. I think the best way to help you is refer to an existing reference design. The reference design will show you how to configure MAC IP register and also have example on how to generate Ethernet frame packet to MAC IP.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20016.pdf

Thanks.

Regards,

dlim