Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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On the MAX 10 device (10 M 08 series), we created a project in Quartus with VCCIO = 2.5 V in VCCIO 1 A / VCCIOB bank. However, 3.3 V is connected to VCCIO1A / VCCIOB on the actual machine. In this case, what kind of risk do you have?

Blues-sptn
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SreekumarR_G_Intel
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Hello, Thank you for the question , Let me rephrase your question to make sure i understood correctly, In quartus project assignment you mention as 2.5V as VCCIO whereas you connected the VCCIO as 3.3V, correct ? if yes , you would like to make sure the VIL/VIH and VOL and VOH is compatibility between the interfaced input and output. if no, can you please clarify? Thank you , Regards, Sree
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Blues-sptn
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Hello!

It was not an confusing expression.

The purpose of the question is as per recognition.

Thank you for your response.​

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