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On my stratix 10 devkit, the FPGA in the JTAG chain has name "ND4_EMU". What does that mean?

VBart
Beginner
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YuanLi_S_Intel
Employee
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Hi Vuk Bartulovic, May i know how do you get this? Also, can the development kit be programmed? Have you tested to program with .sof file? Regards, YL
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VBart
Beginner
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Hello YL,

 

Here is the chain of event, I used s10gx_pcie_devkit_revD.pdf for the schematic of the board.

 

  1. Until recently I had the bts_config.sof working with the bts program. I was able to turn on and off leds. The board was working then.
  2. I was doing an audit on the heating generated from the FPGA by disconnecting the fan and checking the temperature with the bts program. The temperature rose to 60oC, way below the absolute maximum ratings. It's around that time that I noticed the LEDs on the daughter card were no longer lit. That indicated that the 2.5V supply was not there anymore on the board. Altought, the Stratix 10 in the JTAG chain was still normal and was able to program it.
  3. I located the voltage regulator 2.5V (U74) on page 43 of the schematic. I check the ENA pin and it was set to a constant LOW.

I try to force the ENA to be high (3.3V) by putting 0 ohms resistor R502. On power up, that burned the CPLD MAX V for some

reason.

forIntel.PNG4. Then, I remove 0 ohms resistor R502 and took out MAX V CPLD from JTAG chain with switch under the board. At that point I was still able to program the FPGA with the bts_config.sof and I was also checking the sequencer with the USB to PMBUS master cable that came with the kit.

 

5, After some time of monitoring the sequencer with the LTpowerplay program, the MAX V CPLD started to smoke again for no apparent reason. It's only then that I scan the JTAG chain and saw the Stratix 10 was now named "ND4_EMU".

 

What does "ND4_EMU" means?

 

Thanks,

 

 

 

 

 

 

 

 

 

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YuanLi_S_Intel
Employee
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I believe this is the thing you obtained when the MAX V CPLD is faulty. By right it should be showing Stratix 10 like what you had previously.
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