Error (10232): Verilog HDL error : index 22 cannot fall outside the declared range [21:0] for vector "address"

[CSoti]

I am using Quartus Prime Lite Edition 18.1 to generate a system that includes a Platform designer system with Avalon MM Master-Slave interface. Every time I use more than 2 slaves I get the following error.

Error (10232): Verilog HDL error at platform_designer_mm_interconnect_0_router.sv(194): index 22 cannot fall outside the declared range [21:0] for vector "address"

It seems that there is an error in the automatically generated verilog code.

The address bus range for all slaves is equal and defined by a generic. The address space defined in platform designer is well within the limits of the master.

What should I be looking at? I have found questions about the same error for various versions of Quartus but not a clear remedy (apart from removing slaves and that is not an option).

[sstrell]

Without seeing the system or code (for a custom component?), it's really hard to tell what's going on here. Can you provide?

#iwork4intel

[Vicky1]

Hi,

Please check the below solution & let me know, how it works for you,

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05272012_45.html

As mentioned in previous post, if possible provide project file.

Regards,

Vikas

[CSoti]

The above solution did not apply to my project. However, I removed a peripheral and with some adjustments in the avalon mm wrapper the project passes synthesis. For the time being the project is stable. It remains to be seen if it will remain so when I add the rest of the peripherals again.

[CSoti]

Coming back to this issue that remains unresolved. I added another MM Slave and got the same problem:

Info (12128): Elaborating entity "stamp3_platform_designer_mm_interconnect_0_router" for hierarchy "stamp3_platform_designer:inst_stamp3_platform_designer|stamp3_platform_designer_mm_interconnect_0:mm_interconnect_0|stamp3_platform_designer_mm_interconnect_0_router:router"

Error (10232): Verilog HDL error at stamp3_platform_designer_mm_interconnect_0_router.sv(195): index 22 cannot fall outside the declared range [21:0] for vector "address"

Error (12152): Can't elaborate user hierarchy "stamp3_platform_designer:inst_stamp3_platform_designer|stamp3_platform_designer_mm_interconnect_0:mm_interconnect_0|stamp3_platform_designer_mm_interconnect_0_router:router"

The problematic lines of code in stamp3_platform_designer_mm_interconnect_0_router.sv are these:

 always @* begin

    src_data  = sink_data;

    src_channel = default_src_channel;

    src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;

    // --------------------------------------------------

    // Address Decoder

    // Sets the channel and destination ID based on the address

    // --------------------------------------------------

  // ( 0x0 .. 0x400 )

  if ( {address[RG:PAD0],{PAD0{1'b0}}} == 23'h0  ) begin <-- Line 195

      src_channel = 4'b1000;

      src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;

  end

  // ( 0x400 .. 0x400400 )

  // ( no optimization for non-address-span aligned address range )

  if ( ( ( sink_data[PKT_ADDR_H:PKT_ADDR_L] >= 'h400) && (sink_data[PKT_ADDR_H:PKT_ADDR_L] < 'h400400) ) 

       ) begin

      src_channel = 4'b0100;

      src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;

      src_data[PKT_ADDR_H:PKT_ADDR_L] = sink_data[PKT_ADDR_H:PKT_ADDR_L] - 'h400;

  end

  // ( 0x440 .. 0x100440 )

  // ( no optimization for non-address-span aligned address range )

  if ( ( ( sink_data[PKT_ADDR_H:PKT_ADDR_L] >= 'h440) && (sink_data[PKT_ADDR_H:PKT_ADDR_L] < 'h100440) ) 

       ) begin

      src_channel = 4'b0010;

      src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;

      src_data[PKT_ADDR_H:PKT_ADDR_L] = sink_data[PKT_ADDR_H:PKT_ADDR_L] - 'h440;

  end

  // ( 0x480 .. 0x100480 )

  // ( no optimization for non-address-span aligned address range )

  if ( ( ( sink_data[PKT_ADDR_H:PKT_ADDR_L] >= 'h480) && (sink_data[PKT_ADDR_H:PKT_ADDR_L] < 'h100480) ) 

       ) begin

      src_channel = 4'b0001;

      src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;

      src_data[PKT_ADDR_H:PKT_ADDR_L] = sink_data[PKT_ADDR_H:PKT_ADDR_L] - 'h480;

  end

My main problem is that my master has an address range of 22 bits. It is an external uC that I map as an avalon mm master using a bridge.

I now have 4 mm slaves with an address range from 0x0000 to 0x0047f (well within 22 bits) and I even use the System --> Assign Base Address option in order to fit better the address space.

However the compiler wants to map the addresses in more than 22 bits. Why does this happen and how can I avoid it?

[CSoti]

Problem resolved and it is a quartus software issue.

The problem was caused by the HDL generated files from platform designer. I changed the option to generate the HDL files from VHDL to Verilog and then in quartus I changed the compiler settings for Verilog input to system verilog.

The problem disappeared. Clearly there is a problem with the avalon MM address space interpretation when generating VHDL files.

Problem solved.