Technically it is theoretically possible, given the programming file for a device, reconstruct a functionally equivalent verilog (or vhdl) implementation. It would like like the gate level simulation code that Alteral used to be able to generate for back annotated device simulation.
However the big IF is that you need to know what all the bits in the programming file do; ie how they map to device resources. Altera has (never?) provided this to my knowledge which means from a practical perspective it can't be done.
I suppose if you were a large enough / valued enough customer to Altera / Intel you could request the detailed file format under an NDA. But you would likely have to be one of the few very large important customers. Sounds to me like you are not in this category, or you would not be asking the question here on this forum.
