Is there a way to include file with macros and small modules without having to use `include in every file?

[Luis_R_Intel]

Using the Quartus Prime software during the analysis and sythesis stage, we get compilation issues due to undefined text macros. The text macros are declared in their own file and used in other files of our design. The file is included in the project and looks to be analyzed before the other files which use the macros, yet there are still errors saying undefined text macro.

[AnandRaj_S_Intel]

Hi Luis,

1. We need to add the include (macro)files to the project and just compile for Quartus STD & LITE.
2. For Quartus Pro, the compiler to search for macro file and include it during the compile process. No need to use `include in Verilog module. Please check the attached image

We recommend user to just add the `include "define.v" statement to the start of your design file and add macro file in file list.

Hope it helps! Let me know if you need any further assistance.

Regards

Anand

 

[ak6dn]

No. There is no implicit INCLUDE capability in verilog. You need to use `include <file> in each separately compiled verilog module.

[AnandRaj_S_Intel]

Yes, We can use by including the macro files into the file list. If we don't include macro files in file list than we have to `include <file> in each Verilog module. 

Please check the attached image.