How to make RSFEC IP work in Stratix10 device?

[ZLjus]

I am using DEVICE 1SX280HU2F50E1VG. Enabling RS-FEC in the 100GE IP core defining widow places this device in the data path. The problem I have is I can't make the RS-FEC block work. No packets are coming back in a loop back mode. The packets are present and all statistics counter look good when I remove the RS-FEC from the design. Is there something I am missing regarding this IP?

Thank you, Zoran

[Deshi_Intel]

HI,

1. May I know which Quartus version that you are using ?
2. Stratix 10 FPGA contains few Ethernet IP. Are you referring to "low latency 100G Ethernet Intel FPGA IP" or some other Ethernet IP ?
3. Do you encounter the issue in simulation or actual hardware testing ?
4. Can you elaborate further on your loopback testing ?

• Where do you enable the loopback path ?
  • Do you observe data transfer on Tx path as you claim there is no data return on Rx path ?

1. Have you tried debug using Ethernet example design that you can generate from Ethernet IP to see whether issue still persist ?
2. I found some known issues with the RS-FEC feature but not sure related to your issue or not

• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-the-low-latency-100g-ethernet-intel--stratix--10-fpga-i.html
  • https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/why-does-the-generated-example-design-of-100g-ethernet-soft-ip-w.html

Thanks.

Regards,

dlim

[ZLjus]

Is this what you were asking?

[ZLjus]

Hi Dlim,

thanks for the quick response!

Q) May I know which Quartus version that you are using ?:

A) I have used 18.1 and had this proble. Right now I use Q 19.1.0 Build 240 and still have the same problem.

Q) Stratix 10 FPGA contains few Ethernet IP. Are you referring to "low latency 100G Ethernet Intel FPGA IP" or some other Ethernet IP ?:

A) I use low latency 100G Ethernet Intel FPGA IP.

Q) Do you encounter the issue in simulation or actual hardware testing ?

A) I see the problem while testing on hardware, in house developed board.

Q) Can you elaborate further on your loopback testing ?

A) I enable loopback testing by writing 0xF to the appropriate address, 0x300313). The loopback works well with no RSFEC present.

I monitor diagnostics counters for the info regarding the TX and RX frames.

Also I have all relevant signal on the internal logic analyzer so I could see by naked eye what is going on. And what I see there are TX packets but no RX packet.

When with no RSFEC the data packets are visible in both direction.

[Deshi_Intel]

HI, Yes, these are the answers that I am looking for. Do you had a chance to try out with 100G Eth example design to see if the issue still persist ? Also, do take note that RS-FEC block had extra IO PLL to clock it. I presume you had provided correct input clock to the 100G IP, clk_ref pin ? Can you probe reg address 0x322 PHY_CLK bit[2:1] to see whether RS-FEC PLL is locked ? Expected value of 1 Lastly, do you still encounter this issue when internal loopback is disabled (meaning normal external data traffic transaction) ? Thanks. Regards, dlim