10AX066 A10 FPGA transeciever calibration problem:PreSICE nerver relese internal bus

[XZilo]

A10GX series FPGA: Manual xcvr_phy said that transeciever must have a clock before loading the program, otherwise it needs to recalibrate transeciever, but I encountered a problem when performing JESD204B transmission channel calibration.

According to the manual xcvr_phy p558, the first step is to request internal bus arbitration. However, the application was unsuccessful, the bus was always occupied by PreSICE, and the 0x281 register status register showed that the transceiver Tx and Rx calibration was not completed.

[Deshi_Intel]

HI,

May I know do your issue recover after you perform another round of transceiver reset to trigger the calibration process again ?

There are couple of reasons that may affect transceiver power on calibration

• DO you have free running 100Mhz-125MHz clock source supply to FPGA clkusr pin ?
• Do your Quartus design contains PCIe ?
• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2016/why-doesn-t-the-gen3-stratix-v-pcie-hip-start-flow-control-initi.html
• Do your board system level trigger FPGA transceiver channel reset in the middle of transceiver power on calibration that may screw up the calibration process ?

Also, what's the status of CDR lockedtodata signal ? Is it asserted high ?

Thanks.

Regards,

dlim