After simulating stratix10 emif Ip, I found if I try to do simulation for more no. packets then an error message appears. After further debugging I found the issue is with one of library created by quartus.

[DChak3]

I am using ncsim tool for simulation. If i try for less packets lets say 50 it goes well. but for more transaction is shows error. I found the error is caused by one of library names fouteenm_ver. Also I tried for higher version 19. there during library compilation itself this particular library shows error and exit.

[Deshi_Intel]

HI,

Looks like there is some compatibility issue with the simulator.

1. May I know are you using NCSIM v15.2 ?
2. Which EMIF protocol that you are using ?
3. Is the sim error coming from your own EMIF design or EMIF example design ? Else can you try out EMIF example design to see if you can duplicate the issue ?

Thanks.

Regards,

dlim

[DChak3]

HI dlim

Thanks for the response.

1. I am using NCSIM version- Cadence /Incisiv-15.20.018
2. EMIF protocol- DDR4, stratix10, DQ bits 64, hard phy only
3. Yes its from custom emif design. But the error message is residing in the library file generated by the quartus tool.

The error seems to be linked with library names fourteen_ver , as if I grep the error message it resides in the library file. It is encrypted but the message is there.And it appears after 442747ns.

I am not sure it is because of the custom IP or its a bug in emif DDR4 IP.

Also there was a patch released to disable the iossm_buf_cpu.tr file, for 18.1.21 link is below

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/emif/2018/how-can-the-generation-of-the-iossmbfcpucpu-tr-file-be-disabled-.html

But it seems not working still the trace files are generated. I tried with quartus 19 version too, there the libraries are not compiling.

Is there any way to contact intel support directly regarding the issue. We can provide the environment if needed.

[Deshi_Intel]

HI,

I am support AE from Intel and this forum is Intel official platform where we used to support customer issue.

1. Can you try to duplicate the issue using DDR4 example design instead of your own design so that it will be easier for me to debug in house as well ?
2. Also, have you try DDR4 IP design generated with latest Quartus version which is v19.3 ?

Thanks.

Regards,

dlim