FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6355 Discussions

When I run simulation of a rapidio qsys,there is a error occures,but why it is happening?

LWANG128
Beginner
491 Views

When I run simulation of a rapidio qsys,there is a error occures,as this:

Info: Start Nativelink Simulation process

Error: You did not generate the simulation model files or you generated the IP file using an older version of MegaCore which is not supported by RTL NativeLink Simulation

Error: Regenerate the IP and simulation model files using the latest version of MegaCore for RTL NativeLink Simulation flow to function correctly

Error: NativeLink simulation flow was NOT successful

0 Kudos
2 Replies
Vicky1
Employee
282 Views

Hi,

Which Quartus edition & version are you using?

Have you tried by regenerating the IP & simulation model for that IP in presently used quartus tool?

Could you provide *.qar project file ('Project ' Menu->'Archive Project') replication purpose?

Regards,

Vicky

 

0 Kudos
Vicky1
Employee
282 Views

Hi,

May I know any update?

Regards,

Vicky

 

0 Kudos
Reply