About the clk scheme of the cyclone 10 GX development kit

[ZC0001]

Hi, all

On Cyclone® 10 GX Development Kit Board,there are two clk net schemes for FPGA，one is using Si5340 and another is using Si53307-B-GM and Si5332A-C-GM2R . I want to know why there are two schemes? Can i use only one Si5340 to generate 644.53125MHz，125MHz and 100MHz instead of using Si53307-B-GM and Si5332A-C-GM2R？

Looking forward your reply.

Thanks.

[Deshi_Intel]

HI,

You can refer to dev kit user guide doc page 26 - figure 5 clock distribution to understand the clock generator chip connection

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-c10-gx-fpga-devl-kit.pdf

Different clock generator chip is used to provide clock source to different FPGA pin location.

• You can find detail connection in dev kit schematic as well

So in the end it's really depend on which FPGA pin that you plan to use and then you can check which clock generator chip is used to clock your FPGA pin accordingly

Thanks.

Regards,

dlim

[Deshi_Intel]

HI,

I have not hear back from you for quite sometime.

Hopefully my earlier explanation is helpful to you.

For now, I am setting this case to closure.

Thanks.

Regards,

dlim

[ZC0001]

Hi,

I am so sorry for not reply in time.

Thanks for your kindly help.

I have chosen Si5340 to generate clks for refclk of xcvr and EMIF.

Best Regards.

[Deshi_Intel]

np and good luck in working your project :)