We developed a board containing a MAX II device. (EPM240T100) However, this device seems to be very sensitive for ESD. Shooting at the enclosure if enough to make things go wrong. The board also contains an STM32H7 running at 450MHz. This part is not affected by the ESD event at all.
Details about the CPLD implementation:
-4 layer board
-VCCio and VCCint: 100nF for each pin. (very close to the device)
-Output wide chip enable has not been used has been disabled in the quartus software. The same for RST.
-Unused pin's configured as output driving GND.
-No global clocks.
-Pull up and Pull down resistors on JTAG signal
-The logic contains a few registers with buffers connecting the outputs to pins on the device.
-We can also read the status of those registers.
What we see after an ESD event:
-Some outputs go low.
-When we read those outputs by reading back the register who is supposed to drive the output, they are being read as 1.
We have written different versions of the same VHDL code in an attempt to corner the problem.
-We have disable all external signals. (Hard wiring and by changing the VHDL code.) But nothing seems to bring me any closer to the problem at hand. The sensitivity to ESD seems to suggest that something is floating inside the device.
Best regards, H
