I am trying to incorporate in Quartus II project a IP In-System Sources and Probes with a port size (source / probe) of 512 bits [511..0], but when compiling the following error occurs:

[VCarr5]

Error (10652): VHDL Assertion Statement at altsource_probe_body.vhd(451): assertion is false - report "SOURCE_WIDTH must be less than and equal to 511 and greater than and equal to 0" (FAILURE or ERROR).

Although the documentation indicates that a 512-bit size port can be created, I can only make them of size 511.

What can be the cause? bug?

[RichardTanSY_Intel]

Hi, may I know which document that you refer to that indicates a 512-bit size port can be created?

[VCarr5]

In Intel® Quartus® Prime StandardEdition Handbook Volume 3 (https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/Power_Estimation/qts-qps-5v3.pdf), page 53 say:

"...Especify the desired parameters for your custom IP variation.

You can specify up toup to 512 bits for each source. Your design may include up to 128 instances of thisIP core..."

[RichardTanSY_Intel]

May I know which Quartus version are you using?

[VCarr5]

I am using Quartus Prime version 19.1.0 (build 670 09/22 2019) SJ Lite Edition.

I have tried with previous versions under Windows and Linux systems but this problem is still there ..

[RichardTanSY_Intel]

0:511 equates to 512 bits. The count starts from 0.

You may see other Quartus version with port width 0:512, engineering confirm that 0:512 is a bug. Correct fix should be 0:511.

[VCarr5]

Of course, I assume that the port range is 0 index based. But the size and range of the source / probe ports is automatically generated by the IP Catalog Editor tool (MegaWizard Megafuntions in versions <14).

I have performed the following tests:

CASE OK: an In-System source of 511 bits wide its range should be [0..510]:

IP Catalalog -> [...] -> Altera In-System Sources & Probes.

Insert the IP variation into a test design and add some simple logic:

Results:

Analysis & Elaboration → OK!

Analysis & Synthesis → OK!

Compitation → OK!

Programation in FPGA → OK! (Family: Cyclone IV E Device: EP4CE22F17C6 )

Test hardware In-System Sources & Probes Editor → OK!

Test hardware via TCL scripting → OK!

CASE KO:

Now I am going to create a 512-bit wide In-System source, its range should be [0.511].

IP Catalalog -> [...] -> Altera In-System Sources & Probes.

Insert the IP variation into a test design and add some simple logic:

Results:

Analysis & Elaboration → OK!

Analysis & Synthesis → OK!

Compitation → OK!

Programation in FPGA → OK! (Family: Cyclone IV E Device: EP4CE22F17C6 )

Test hardware In-System Sources & Probes Editor → KO!

Test hardware via TCL scripting → KO!

←End test cases

I think I am making proper use of the Quartus tools, for example IP Catalog Editor makes sure to validate the entries for example:

I may be wrong but it seems to me that the origin of these problems may be in the archive altsource_probe_top.v. But this file is owned by (C) 2001-2019 Intel Corporation and the terms of the license prohibit any modification.

[RichardTanSY_Intel]

The unexpected JTAG communication error can occur because the board is not powered on, the programming hardware is not connected, there is a problem with the circuit board, or you did not SRAM Object File (.sof).

Make sure the circuit board is powered on, the programming hardware is connected properly, and download the current SOF.